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21. 发明专利

JP2013243665A Circuit and method for generating period control signal, microscope, and method for controlling microscope 有权
标题翻译：用于产生周期控制信号的电路和方法，微阵列和控制微观方法
公开(公告)号：JP2013243665A
公开(公告)日：2013-12-05
申请号：JP2013101996
申请日：2013-05-14
申请人： Leica Microsystems Cms Gmbh , ライカマイクロシステムスツェーエムエスゲーエムベーハー
发明人： THORSTEN KOESTER
IPC分类号： H03K5/15 , G02B21/00 , G06F1/06 , H03K23/00
CPC分类号： H03K5/15 , G02B21/16 , H03K5/131 , H03K5/15013
摘要： PROBLEM TO BE SOLVED: To provide a circuit and a method to generate a period control signal.SOLUTION: The circuit generates a period control signal for a microscope especially so as to generate a plurality of control signals as flexibly as possible. The circuit is configured to generate and output at least two control signals which are mutually phase-shifted. A circuit (2) has a plurality of generation circuits (1), each of which is provided for each control signal (PULSE_OUT) outputted by the circuit (2). Each of the generation circuits (1) has a phase value memory (4) for storing a phase value which defines a phase shift, has a start input unit (6), and generates the control signal (PULSE_OUT) which is phase-shifted for an amount defined by the phase value in accordance with application of a start level to the start input unit (6). The start input unit (6) of the generation circuit (1) is connected together with a start circuit (8) for simultaneously outputting the start level to the generation circuit.
摘要翻译：要解决的问题：提供一种产生周期控制信号的电路和方法。解决方案：电路产生用于显微镜的周期控制信号，特别是以尽可能灵活地产生多个控制信号。电路被配置为产生并输出相互相移的至少两个控制信号。电路（2）具有多个产生电路（1），每个产生电路（1）被提供给由电路（2）输出的每个控制信号（PULSE_OUT）。每个发生电路（1）具有用于存储定义相移的相位值的相位值存储器（4），具有起始输入单元（6），并且生成相移的控制信号（PULSE_OUT）根据启动电平对启动输入单元（6）的应用，由相位值定义的量。生成电路（1）的起始输入单元（6）与用于同时向起始电路输出开始电平的启动电路（8）连接。

22. 发明专利

JPWO2009133658A1 多信号スイッチ回路、電流スイッチセル回路、ラッチ回路、電流加算型ＤＡＣ、及び半導体集積回路、映像機器、通信機器审中-公开
公开(公告)号：JPWO2009133658A1
公开(公告)日：2011-08-25
申请号：JP2010510022
申请日：2009-04-06
申请人：パナソニック株式会社
发明人：美智子徳丸 , 美智子徳丸 , 平治生駒 , 平治生駒
IPC分类号： H03K5/00 , H03K3/037 , H03M1/08 , H03M1/74
CPC分类号： H03M1/0836 , H03K5/15013 , H03K17/002 , H03M1/0624 , H03M1/745
摘要： 4つの入力信号IN1〜IN4を用いる多信号スイッチ回路において、4入力ラッチ回路3bが配置される。この4入力ラッチ回路3bは、前記4つの信号IN1〜IN4のうち1つが”L”、3つが”H”を取るときには、4つのNAND回路6’’で構成される。各NAND回路6’’では、その出力は、各々、前記4つの入力信号IN1〜IN4のうちの1つに接続され、その出力に接続された信号以外の残る3つの信号を入力とする。従って、3つ以上の入力信号を持つ多信号スイッチ回路においても、出力すべき多信号間のタイミングエラーが有効に防止される。

23. 发明专利

JP2007295562A Phase splitter 审中-公开
标题翻译：相分离器
公开(公告)号：JP2007295562A
公开(公告)日：2007-11-08
申请号：JP2007108613
申请日：2007-04-17
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIN EISHOKU
IPC分类号： H03K5/15 , G06F1/06 , G11C11/4076
CPC分类号： H03K5/15013 , H03K5/1515
摘要： PROBLEM TO BE SOLVED: To provide a phase splitter which divides an input clock into multiple clock signals and minimizes a skew between the clock signals for a PVT change. SOLUTION: This phase splitter inputs an external clock and generates a first internal clock and a second internal clock with a phase difference of 180°. This phase splitter also comprises a first buffer for buffering and outputting the external clock signal, an inverter for inverting and outputting the external clock signal, a second buffer for buffering the output signal in the inverter, a first interpolation signal generator for inverting and outputting the external clock signal and a second interpolation signal generator for inverting and outputting the output signal in the inverter. In addition, this phase splitter interpolates signals output from the first buffer and second interpolation signal generator to produce the first internal lock signal and interpolates those from the second buffer and first interpolation signal generator to produce the second internal clock, resulting in skew minimization via the splitter. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种将输入时钟分为多个时钟信号并最小化用于PVT变化的时钟信号之间的偏差的相位分离器。
解决方案：该分相器输入外部时钟，并产生第一个内部时钟和第二个内部时钟，相位差为180°。该分相器还包括用于缓冲和输出外部时钟信号的第一缓冲器，用于反相和输出外部时钟信号的反相器，用于缓冲反相器中的输出信号的第二缓冲器，用于反相和输出外部时钟信号的第一内插信号发生器外部时钟信号和第二内插信号发生器，用于反相和输出反相器中的输出信号。此外，该分相器插值从第一缓冲器和第二内插信号发生器输出的信号，以产生第一内部锁定信号，并且内插来自第二缓冲器和第一内插信号发生器的信号，以产生第二内部时钟，从而产生经由分离器。版权所有（C）2008，JPO＆INPIT

24. 发明专利

JP2007215213A System and method for multiple-phase clock generation 审中-公开
标题翻译：多相时钟生成系统与方法
公开(公告)号：JP2007215213A
公开(公告)日：2007-08-23
申请号：JP2007065275
申请日：2007-03-14
申请人： Silicon Image Inc , シリコン・イメージ,インコーポレーテッド
发明人： KIM OOK , LI HUNG SUNG , LEE INYEOL , KIM GYUDONG , LEE YONGMAN
IPC分类号： H03K5/15 , G06F1/06 , H03K21/00 , H03K23/00 , H03K23/54 , H03L7/089 , H03L7/099
CPC分类号： H03K23/542 , G06F1/06 , H03K5/15013 , H03L7/0891 , H03L7/0995
摘要： PROBLEM TO BE SOLVED: To provide a method for multiple-phase clock generation. SOLUTION: In one embodiment, a multiple-stage voltage controlled oscillator ("VCO") (302) transmits a plurality of clock phases (ck0-ck5) to a clock divider (304) which produces the desired number of clock phase outputs. The clock divider (304) in this embodiment includes a state machine, e.g., a modified Johnson counter (316), that provides a plurality of divided down clock phases, each of which is connected to separate modified shift registers (306-314). Each modified shift register contains D-type flip-flops and each D-type flip-flop provides a separate clock phase output. In one embodiment, the number of clock phase outputs of the multiple-phase clock is a function which multiplies the number of VCO clock phases by the number of desired states in the modified Johnson counter. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于多相时钟产生的方法。解决方案：在一个实施例中，多级压控振荡器（“VCO”）302将多个时钟相位（ck0-ck5）发送到产生期望数量的时钟相位的时钟分频器（304）输出。本实施例中的时钟分频器（304）包括状态机，例如经修改的约翰逊计数器（316），其提供多个划分的下降时钟相位，每个相位分别与分离的修改的移位寄存器（306-314）连接。每个修改的移位寄存器包含D型触发器，每个D型触发器提供单独的时钟相位输出。在一个实施例中，多相时钟的时钟相位输出的数量是将VCO时钟相位数乘以经修改的约翰逊计数器中的期望状态的数量的函数。版权所有（C）2007，JPO＆INPIT

25. 发明专利

JP2006253945A Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：JP2006253945A
公开(公告)日：2006-09-21
申请号：JP2005065985
申请日：2005-03-09
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： TAKAHASHI AKIRA , MIYAKE JIRO , MORIKAWA TORU
IPC分类号： H03K3/02 , H03K5/153
CPC分类号： H03K5/156 , G06F1/04 , H03K5/15013
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of supplying clock signals with two kinds of frequencies through one clock signal line at the same time, capable of capturing data at an interval shorter than a half period, and capable of selecting a function execution means for executing asynchronous resetting through one reset signal line depending on a potential level of a reset signal. SOLUTION: The semiconductor integrated circuit device includes: a first function execution means including at least one latch means or over for capturing data when a potential level of a clock signal changes to a potential level from a potential level less than a threshold value of a particular potential level to a potential level being the threshold value or over; a second function execution means including at least one latch means or over for capturing data when a potential level of the clock signal changes to a potential level from a potential level less than a threshold value of a new particular potential level, smaller than the threshold value of the first function execution means, to a potential level being the new threshold value or over; a clock supply means for generating clock pulses for repeating at least two high potential levels or over and a potential level zero and supplying the clock to the first and second function execution means; and a voltage application means for applying at least two ore more high potential level values and a potential level zero to the first and second execution means and the clock supply means. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供能够同时通过一个时钟信号线提供具有两种频率的时钟信号的半导体集成电路器件，能够以短于半周期的间隔捕获数据，并且能够选择功能执行装置，用于根据复位信号的电位电平通过一个复位信号线执行异步复位。解决方案：半导体集成电路器件包括：第一功能执行装置，其包括至少一个锁存装置或用于当时钟信号的电位电平从小于阈值的电位电平变为电位电平时捕获数据具有潜在水平的潜在水平为阈值或以上; 第二功能执行装置，其包括至少一个锁存装置或者用于当时钟信号的电位电平从小于新特定电位电平的阈值的电位电平变为电位电平时捕获数据，小于阈值第一功能执行装置的潜在等级为新的阈值或以上; 一个时钟提供装置，用于产生用于重复至少两个高电位电平或超过电平电平零的时钟脉冲，并将时钟提供给第一和第二功能执行装置; 以及电压施加装置，用于向第一和第二执行装置和时钟提供装置施加至少两个更高的电位电平值和电位电平零。版权所有（C）2006，JPO＆NCIPI

26. 发明专利

JP3555077B2 The programmable logic device of the clock distribution circuit 有权
公开(公告)号：JP3555077B2
公开(公告)日：2004-08-18
申请号：JP2000093234
申请日：2000-03-30
申请人： Necエレクトロニクス株式会社
发明人：裕隆中野
IPC分类号： G06F1/10 , H03K5/135 , H03K5/15 , H03K19/173
CPC分类号： H03K5/15013

27. 发明专利

JPH11272353A Clock supply circuit and data transfer circuit 失效
标题翻译：时钟供电电路和数据传输电路
公开(公告)号：JPH11272353A
公开(公告)日：1999-10-08
申请号：JP7082098
申请日：1998-03-19
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIRAISHI MIKIO
IPC分类号： G06F1/10 , G06F5/10 , H03K5/135 , H03K5/15
CPC分类号： G06F5/10 , G06F1/10 , H03K5/135 , H03K5/15013
摘要： PROBLEM TO BE SOLVED: To prevent the malfunction of a circuit owing to a clock skew by constituting a clock supply circuit of the buffers of plural stages, which are connected in series, and supplying a clock signal whose phase is delayed more and which is taken out through the buffer of a larger number of stages to a data signal input/output circuit belonging to a nearer group.
SOLUTION: An input data signal D
0 is inputted to a flip flop 1a, a data signal D
1 being the output is inputted to a flip flop 1b and a data signal D
2 being the output is inputted to a flip flop 1c. First to third clock signals P
1 -P
3 are inputted to the flip flops 1c-1a of third to first stages. A clock supply circuit supplying the clock signals P
1 -P
3 is constituted of the clock buffers 2a-2c of first to third stages, which are sequentially connected in series. An input clock signal P
0 is inputted to the clock buffer 2a of the first stage. The clock signals P
1 -P
3 are set to be the output signals of the clock buffers 2a-2c.
COPYRIGHT: (C)1999,JPO
摘要翻译：要解决的问题：为了通过构成串联连接的多级的缓冲器的时钟供给电路并且提供相位被延迟更多的时钟信号并且被采用来防止由于时钟偏移引起的电路的故障通过更多级的缓冲器输出到属于更近组的数据信号输入/输出电路。解决方案：输入数据信号D0被输入到触发器1a，作为输出的数据信号D1被输入到触发器1b，并且作为输出的数据信号D2被输入到触发器1c。第一至第三时钟信号P1-P3被输入到第三至第一级的触发器1c-1a。提供时钟信号P1-P3的时钟供给电路由顺序地串联连接的第一至第三级的时钟缓冲器2a-2c构成。输入时钟信号P0被输入到第一级的时钟缓冲器2a。时钟信号P1-P3被设置为时钟缓冲器2a-2c的输出信号。

28. 发明专利

JPS58212217A Waveform converter 失效
标题翻译：波形转换器
公开(公告)号：JPS58212217A
公开(公告)日：1983-12-09
申请号：JP9048783
申请日：1983-05-23
申请人： Toshiba Corp
发明人： SHIGEMATSU TOMOHISA , SUZUKI YASOJI
IPC分类号： H03K5/1532 , H03K5/15
CPC分类号： H03K5/15013
摘要： PURPOSE:To miniaturize an integrated circuit, by obtaining a response pulse in synchronizing with the leading or trailing of an input signal with a clocked inverter comprising MOS transistors(TRs). CONSTITUTION:A level in common for the input signal Si and an output Si' of a clock inverter 33 exists only for a section of a pulse width of a clock pulse CP when the input signal fluctuates, and a negative pulse P2 in response to the leading of the signal Si is obtained from an output of an NAND gate 34. When the input signal Si of the inverter 33 fluctuates from ''1'' to ''0'' in synchronizing with the leading of the clock pulse, a positive pulse P3 in response to the trailing of the signal Si is obtained from an output of an NOR gate 35. Further, an output signal P2 of the NAND gate 34 and an output signal P3 of the NOR gate 35 are inverted respectively with inverters 36 and 37 and pulses P1 and P4 are obtained.
摘要翻译：目的：为了使集成电路小型化，通过用包括MOS晶体管（TRs）的时钟反相器获得与输入信号的前导或后沿同步的响应脉冲。构成：输入信号Si和时钟反相器33的输出Si'的共同电平仅在输入信号波动时存在于时钟脉冲CP的脉冲宽度的部分，响应于时钟脉冲CP的负脉冲P2 信号Si的引导从NAND门34的输出获得。当反相器33的输入信号Si与时钟脉冲的引导同步地从“1”波动到“0”时，正的从或非门35的输出获得响应于信号Si的尾部的脉冲P3。此外，与非门34的输出信号P2和或非门35的输出信号P3分别与反相器36和 37，获得脉冲P1和P4。

29. 发明专利

JPS58194431A Digital controller 失效
标题翻译：数字控制器
公开(公告)号：JPS58194431A
公开(公告)日：1983-11-12
申请号：JP2712883
申请日：1983-02-22
申请人： Ibm
发明人： JIERAADO EI BUENESUKII , NANDOO JII TOOMA , MOISESU KEESESU
IPC分类号： H03K19/177 , G06F9/22 , H03K5/15
CPC分类号： H03K5/15013 , G06F9/223

30. 发明专利

JPS5120144B1 JPS5120144B1 - 失效
公开(公告)号：JPS5120144B1
公开(公告)日：1976-06-23
申请号：JP1830971
申请日：1971-03-27
IPC分类号： G11C11/4076 , H03K3/353 , H03K3/354 , H03K5/02 , H03K5/04 , H03K5/05 , H03K5/15 , H03K5/151 , H03K5/156
CPC分类号： G11C7/222 , G11C7/04 , G11C11/4076 , H03K3/353 , H03K3/354 , H03K5/023 , H03K5/04 , H03K5/05 , H03K5/15013 , H03K5/1504 , H03K5/1515

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