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21. 发明专利

JP2011054658A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2011054658A
公开(公告)日：2011-03-17
申请号：JP2009200425
申请日：2009-08-31
申请人： Toshiba Corp , 株式会社東芝
发明人： NISHIHARA KIYOHITO
IPC分类号： H01L27/115 , H01L21/8247 , H01L29/788 , H01L29/792
CPC分类号： H01L21/76819 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11565 , H01L27/11568
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory capable of securing a short-margin between a contact and an active area.
SOLUTION: In the nonvolatile semiconductor memory 1, STIs are formed to the upper layer of a silicon substrate, and the upper layer of the silicon substrate is partitioned into a plurality of active areas AA that extend in the Y direction. Bit-line contacts CB are formed on the active areas AA, and the lower ends thereof are connected to the active areas AA. Here, the bit-line contacts CB are arranged zigzag. The top faces of parts 7 have positions in the Y direction which is identical to those of the parts 6 of one active areas AA as parts of the other active areas AA arranged adjacent to one active areas AA, and the positions are disposed to the parts lower than the top faces of the parts 6 connecting the bit-line contacts CB in one of the active areas AA.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够确保接触和有效区域之间的短距离的非易失性半导体存储器。解决方案：在非易失性半导体存储器1中，STI形成在硅衬底的上层，并且硅衬底的上层被划分成在Y方向上延伸的多个有源区AA。位线触点CB形成在有源区域AA上，其下端连接到有源区域AA。这里，位线接点CB以Z字形排列。部件7的顶面在Y方向具有与一个有效区域AA的部分6相同的位置，作为与一个有效区域AA相邻设置的其它有效区域AA的部分，并且位置被布置在部件低于连接有源区域AA之一中的位线触点CB的部件6的顶面。版权所有（C）2011，JPO＆INPIT

22. 发明专利

JP2011018755A Nonvolatile semiconductor storage device and method of manufacturing the same 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：JP2011018755A
公开(公告)日：2011-01-27
申请号：JP2009161982
申请日：2009-07-08
申请人： Toshiba Corp , 株式会社東芝
发明人： KAWADA NOBUHITO , NISHIHARA KIYOHITO
IPC分类号： H01L27/115 , H01L21/8247 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device which can be improved in integration and reduced in cost, and to provide a method of manufacturing the same.SOLUTION: The nonvolatile semiconductor storage device includes a semiconductor substrate 10 including a plurality of diffusion layers, a first memory film 15 formed on the semiconductor substrate, a plurality of first gate electrodes WL1 and a first selection gate electrode SG1 formed on the first memory film, a second memory film 24 formed on the plurality of first gate electrodes and the first selection gate electrode, a first semiconductor layer 25 formed on the second memory film, a third memory film 30 formed on the first semiconductor layer, and a plurality of second gate electrodes and a second selection gate electrode SG2 formed on the third memory film.
摘要翻译：要解决的问题：提供可以提高集成度和降低成本的非易失性半导体存储装置，并提供其制造方法。解决方案：非易失性半导体存储装置包括：半导体衬底10，包括多个扩散形成在半导体衬底上的第一存储膜15，形成在第一存储膜上的多个第一栅电极WL1和第一选择栅电极SG1，形成在多个第一栅电极上的第二存储膜24和第一存储膜选择栅电极，形成在第二存储膜上的第一半导体层25，形成在第一半导体层上的第三存储膜30，以及形成在第三存储膜上的多个第二栅电极和第二选择栅电极SG2。

23. 发明专利

JP2010212604A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010212604A
公开(公告)日：2010-09-24
申请号：JP2009059729
申请日：2009-03-12
申请人： Toshiba Corp , 株式会社東芝
发明人： IZUMI TATSUO , NITTA HIROYUKI , KAMIGAICHI TAKESHI , NISHIHARA KIYOHITO , ARAI FUMITAKA
IPC分类号： H01L27/00 , H01L21/768 , H01L21/8247 , H01L23/522 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that is prevented from increasing in the chip area, and to provide a method of manufacturing the device.
SOLUTION: The semiconductor device includes a semiconductor substrate 100, having a diffusion region 101a on its surface; an interlayer insulating film 107 covering the semiconductor substrate 100; a semiconductor layer 108, formed on the interlayer insulating film 107 and having a diffusion region 109a on its surface; a source line plug 116a formed in a through-hole 119a, penetrating the interlayer insulating film 107 and the semiconductor layer 108 and coming into contact with the diffusion region 101a, and also having its side surface partially in contact with the diffusion region 109a; and a sidewall insulating film 117a, interposed between the source line plug 116a and interlayer insulating film 107, as well as, interposed between the source line plug 116a and semiconductor layer 108, excluding a part where the source line plug 116a comes into contact with the diffusion region 109a.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种防止芯片面积增加的半导体器件，并提供一种制造器件的方法。解决方案：半导体器件包括其表面上具有扩散区域101a的半导体衬底100; 覆盖半导体衬底100的层间绝缘膜107; 半导体层108，其形成在层间绝缘膜107上并且在其表面上具有扩散区域109a; 形成在贯穿层间绝缘膜107和半导体层108并与扩散区域101a接触的通孔119a中的源极线插头116a，并且其侧表面部分地与扩散区域109a接触; 以及设置在源极线插头116a和层间绝缘膜107之间的侧壁绝缘膜117a，并且插入在源极线插塞116a和半导体层108之间，不包括源极线插头116a与其间的接触部分扩散区域109a。版权所有（C）2010，JPO＆INPIT

24. 发明专利

JP2010134983A Depletion-type nand flash memory 审中-公开
标题翻译： DEPLETION型NAND闪存
公开(公告)号：JP2010134983A
公开(公告)日：2010-06-17
申请号：JP2008308607
申请日：2008-12-03
申请人： Toshiba Corp , 株式会社東芝
发明人： MIZUKAMI MAKOTO , NISHIHARA KIYOHITO
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , G11C16/0483 , H01L21/84 , H01L27/11521 , H01L27/11524 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L27/1203
摘要： PROBLEM TO BE SOLVED: To prevent variation in a cell threshold when a depletion-type NAND is read. SOLUTION: The present invention relates to a depletion-type NAND flash memory, in which each of a plurality of depletion-type FETs constituting a NAND string is a transistor whose threshold changes in accordance with a charge quantity in a charge accumulation layer, and an adjacent memory cell storage stores the threshold of a source line side depletion-type FET adjacent to a source line side of a selected depletion-type FET. A control circuit adds a value obtained by adding a particular potential stored in a particular potential storage to a threshold stored in an adjacent memory cell threshold storage to a gate potential of the source line side depletion-type FET, in the read operation. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了防止读取耗尽型NAND时的单元阈值的变化。解决方案：本发明涉及耗尽型NAND闪速存储器，其中构成NAND串的多个耗尽型FET中的每个都是其阈值根据电荷累积层中的电荷量而变化的晶体管并且相邻的存储单元存储器存储与选择的耗尽型FET的源极侧相邻的源极侧耗尽型FET的阈值。在读取操作中，控制电路将存储在特定电位存储器中的特定电位所获得的值与存储在相邻存储单元阈值存储器中的阈值相加到源极侧耗尽型FET的栅极电位。版权所有（C）2010，JPO＆INPIT

25. 发明专利

JP2009076680A Non-volatile semiconductor storage device and its operating method 审中-公开
标题翻译：非挥发性半导体存储器件及其工作方法
公开(公告)号：JP2009076680A
公开(公告)日：2009-04-09
申请号：JP2007244321
申请日：2007-09-20
申请人： Toshiba Corp , 株式会社東芝
发明人： NISHIHARA KIYOHITO , ARAI FUMITAKA
IPC分类号： H01L21/8247 , G11C16/02 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7881 , G11C11/5628 , G11C11/5642 , G11C2211/5621 , H01L27/115 , H01L27/11521
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor storage device capable of setting a plurality of positive levels having positive thresholds for storing information and a plurality of negative levels having negative thresholds, and to provide an operation method of the device. SOLUTION: The non-volatile semiconductor storage device according to one mode is provided with a storage element which is arranged at the first main face side of a semiconductor layer and comprises a charge storage layer having a plurality of positive levels having positive threshold voltages for storing information and a plurality of negative levels having negative threshold voltages and electrodes which are arranged on a second main face side of the semiconductor layer, facing the storage element and applies a voltage converting information accumulated in the negative level into information having a positive threshold voltage. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供能够设置具有用于存储信息的正阈值的多个正电平和具有负阈值的多个负电平的非易失性半导体存储装置，并且提供该装置的操作方法。解决方案：根据一种模式的非易失性半导体存储装置设置有存储元件，该存储元件布置在半导体层的第一主面侧，并且包括具有多个具有正阈值的正电平的电荷存储层用于存储信息的电压和具有负阈值电压的多个负电平和布置在半导体层的第二主面侧上的电极，面对存储元件，并将积极在负电平的电压转换信息施加到具有正的信息阈值电压。版权所有（C）2009，JPO＆INPIT

26. 发明专利

JP2008263029A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2008263029A
公开(公告)日：2008-10-30
申请号：JP2007104072
申请日：2007-04-11
申请人： Toshiba Corp , 株式会社東芝
发明人： MIZUKAMI MAKOTO , NISHIHARA KIYOHITO
IPC分类号： H01L21/8247 , H01L21/3205 , H01L23/52 , H01L27/115 , H01L29/41 , H01L29/423 , H01L29/49 , H01L29/788 , H01L29/792
CPC分类号： H01L27/105 , H01L27/0688 , H01L27/11529 , H01L27/11531 , H01L27/11556
摘要： PROBLEM TO BE SOLVED: To facilitate an electric connection between a memory cell array and a peripheral circuit.
SOLUTION: A semiconductor memory device comprises: a substrate 13 having a memory cell array region and a peripheral circuit region; a memory cell array 11 formed in the memory cell array region, and having a plurality of memory cells laminated in a vertical direction; a peripheral circuit 12 formed in the peripheral circuit region, for supplying an electric signal to the memory cell array 11; a contact 34 formed on an upper face of the memory cell array 11 and electrically connected to the peripheral circuit 12; and a plurality of wiring layers 17 for electrically connecting the memory cell array 11 with the contact 34. The base of the memory cell array 11 is set lower than the base of the peripheral circuit 12.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了便于存储单元阵列和外围电路之间的电连接。解决方案：半导体存储器件包括：具有存储单元阵列区域和外围电路区域的衬底13; 存储单元阵列11，其形成在存储单元阵列区域中，并且具有沿垂直方向层叠的多个存储单元; 外围电路12，形成在外围电路区域中，用于向存储单元阵列11提供电信号; 形成在存储单元阵列11的上表面并电连接到外围电路12的触点34; 以及用于将存储单元阵列11与触点34电连接的多个布线层17.存储单元阵列11的基底设置为比外围电路12的基极低。（C）2009， JPO＆INPIT

27. 发明专利

JP2008066466A Semiconductor memory device, and method of correcting read voltage of the same 审中-公开
标题翻译：半导体存储器件，以及校正其读取电压的方法
公开(公告)号：JP2008066466A
公开(公告)日：2008-03-21
申请号：JP2006241806
申请日：2006-09-06
申请人： Toshiba Corp , 株式会社東芝
发明人： NISHIHARA KIYOHITO , ARAI FUMITAKA
IPC分类号： H01L27/10 , G11C16/04 , G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/105 , G11C16/0483 , G11C16/26 , G11C16/3427 , H01L27/115 , H01L27/11502 , H01L27/11509 , H01L27/11526
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device which can be improved in reliability, and to provide a method of correcting the read voltage of the same which can improve the yield. SOLUTION: The semiconductor memory device comprises a semiconductor memory 12, a corrected voltage memory circuit 19 for storing a corrected voltage Vread' which is a corrected read voltage of the semiconductor memory, and a controller 13 which is so configured as to read out the corrected voltage from the corrected voltage memory circuit and perform a readout operation of the semiconductor memory by the corrected voltage. COPYRIGHT: (C)2008,JPO&INPIT

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