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21. 发明专利

JPS61105144A Pseudo reference burst generator 失效
标题翻译： PSEUDO参考脉搏发生器
公开(公告)号：JPS61105144A
公开(公告)日：1986-05-23
申请号：JP22717384
申请日：1984-10-29
申请人： Nec Corp
发明人： HOTSUTA TOSHITSUNE
IPC分类号： H04J3/14 , H04B7/15 , H04B7/212
摘要： PURPOSE: To transmit a desired control signal to a slave station device and to obtain an economical pseudo reference burst generator by providing a reference burst generating circuit generating a reference burst and a modulation circuit modulating the reference burst and outputting the result and giving an output signal of the modulation circuit to a time division multiple address device as a test signal.
CONSTITUTION: A system clock signal 101 is given to a frame counter 2, a reference burst synthesis circuit 3 and a clock input CLK of a modulation circuit 32 from a system block oscillator 1 being an oscillator of a symbol rate frequency. The system block signal 101 is subject to frequency division and becomes a frame pulse signal 102 corresponding to the TDMA frame period is given to a frame pulse input of a reference burst synthesis circuit 3 from the output TC of the frame counter 2. A burst gate signal 103 corresponding to the reference burst length is given to the modulation circuit 32 from the reference burst synthesis circuit 3, further a transmission data signal 109 is given to the modulation circuit 32 from an OR gate 11 and a reference burst 110 is given to a time division multiple address device (not shown) from the modulation circuit 32.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过提供产生参考脉冲串的参考脉冲发生电路和调制参考脉冲串并输出结果并给出输出信号来获得经济的伪参考脉冲串发生器，从而将所需的控制信号发送到从站设备，作为测试信号的时分多址地址设备。构成：系统时钟信号101被提供给来自系统块振荡器1的帧计数器2，参考突发合成电路3和调制电路32的时钟输入CLK，其是符号速率频率的振荡器。从帧计数器2的输出TC向系统块信号101进行分频，并且将对应于TDMA帧周期的帧脉冲信号102提供给参考突发合成电路3的帧脉冲输入。突发门从参考突发合成电路3向调制电路32提供对应于参考突发长度的信号103，另外从或门11向调制电路32提供传输数据信号109，并将参考突发110给予来自调制电路32的时分多址地址装置（未示出）。

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