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21. 发明专利

JPS5234770A DETECTION CIRCUIT OF MULTIPLE INPUT MAXIMUM VALUE 失效
公开(公告)号：JPS5234770A
公开(公告)日：1977-03-16
申请号：JP9457575
申请日：1975-08-01
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE
发明人： HASEGAWA KOUICHI , IWATA ATSUSHI
IPC分类号： G01R19/165 , G01R19/04 , G06G7/12
摘要： PURPOSE:To obtain a detection circuit of multiple input maximum value which is able to detect the maximum value in linear form at high accuracy even for low signal levels.

22. 发明专利

JPS5234607A MULTIFREQUENCY SIGNAL RECEIVING SYSTEM 失效
公开(公告)号：JPS5234607A
公开(公告)日：1977-03-16
申请号：JP9457275
申请日：1975-08-01
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE
发明人： HASEGAWA KOUICHI , UEKI ISAMU , IWATA ATSUSHI
IPC分类号： H04Q1/45 , H04L27/26 , H04Q1/453
摘要： PURPOSE:In case the working level of flequency isolation filter is different against the input signal composed of different frequency and the adjacent band wave is output with leakage, the malfunction of multifrequency signal receiving equipment can be effectively prevented.

23. 发明专利

JPS5665524A STEP GENERATOR IN MUURULE COMPANDOR 失效
公开(公告)号：JPS5665524A
公开(公告)日：1981-06-03
申请号：JP14042479
申请日：1979-11-01
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： OOHATA MICHINOBU , MATSUMURA TOSHIHIKO , YAMAZAWA MASAO , TANAKA HISAKI , KUROSAWA HIDEYUKI , SASAGAWA MASAAKI , IWATA ATSUSHI
IPC分类号： H03M1/66 , H03M1/76 , H03K13/05
摘要： PURPOSE:To reduce the number of resistances, by removing resistances exclusive use for analog output at bit steal so that the analog output value at bit-steal mode can be delivered, through the analog output value at normal mode shifted by 1/2 of unit interval. CONSTITUTION:Resist R1, R17 at the both ends of series resistor trains R1-R17 are selected with change-over switches SW16 and SW17. At normal mode, SWs 16 and 17 are respectively made to open and close, and a switch decoder 2 delivers control signals X0-X15. On the other hand, at bit-steal mode, switches 16 and 17 are respectively made close and open. Thus, every other switches SW1, SW3,... SW15 are operated with step designation bit stored in a register 1. Accordingly, since resistors for exclusive use for bit steal are not used, the number of resistances and switches can be decreased.

24. 发明专利

JPS5537019A SWITCHED CAPACITOR FILTER 失效
公开(公告)号：JPS5537019A
公开(公告)日：1980-03-14
申请号：JP10968478
申请日：1978-09-08
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： KATOU SEIJI , UENO NORIO , MATSUZAKI SHINPEI , IWATA ATSUSHI
IPC分类号： H03H19/00 , H03H17/02
摘要： PURPOSE:To reduce the delay of signal and obtain the attenuation property of good filtering by carrying out the timing of ON and OFF of the respective stage switch alternatingly. CONSTITUTION:ON and OF of switching of the capacitors of the longitudinally connected integrators 2a, 2b are alternatingly carried out with the sampling of the signals of the respective stage integrators having the phases shifted by using the two phase clock pulses phi1, phi2. Namely, the output of the first stage integrator 2a is sampled by the post integrator 2b after the time of 1/2 clock. The post integrator 2b has the output signal sampled by the first stage integrator 2a through the return circuit after 1/2 clock time. Accordingly, the delay of the signal generated in the respective stages is 1/2 clock time.

25. 发明专利

JPS5827438A PLL CIRCUIT 失效
公开(公告)号：JPS5827438A
公开(公告)日：1983-02-18
申请号：JP12624881
申请日：1981-08-12
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： ITOU AKIHIKO , SAITOU TADAHIRO , FUKUI HIROKAZU , IWATA ATSUSHI , KANEKO TAKAO
IPC分类号： H03L7/093 , H03L7/089 , H03L7/08
摘要： PURPOSE:To make circuit integration easy, by constituting a loop filter with three capacitors the charge/discharge of which is controlled with switches. CONSTITUTION:If the phase of an input signal (c) is delayed than that of an output signal (d) of a voltage controlled oscillator, a transistor Q1 turns on, the potential at an output terinal OUT is risen via a capacitor C2 and a TRQ10 turns on. As a result, the charge of a capacitor C1 is started and control is made so that the oscillated frequency of the voltage controlled oscillator can be increased according to the rise of the potential of the output terminal OUT. If the phase of the signal (d) is led, the potential of the output terminal OUT is decreased via a capacitor C3, a TRQ11 turns on and a charge in the capacitor C1 is discharged, to decrease the oscillated frequency.

26. 发明专利

JPS564814A VOLTAGE DIVIDING CIRCUIT 失效
公开(公告)号：JPS564814A
公开(公告)日：1981-01-19
申请号：JP8041779
申请日：1979-06-26
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： OOHATA MICHINOBU , MATSUMURA TOSHIHIKO , YAMAZAWA MASAO , TANAKA HISATOMO , IWATA ATSUSHI
IPC分类号： G05F1/10 , H03H7/24 , H03M1/74
摘要： PURPOSE:To increase the accuracy of divided voltage, by connecting the return resistor having the same resistance as the resistor network and the reference potential of the opposite polarity as the resistance network via the interlocking switch to the connection point between the voltage division resistance network and ground wiring. CONSTITUTION:One end of the voltage division resistance network RG is connected to the reference voltage Vref of positive or negative polarity via the switch S1, and another end is connected to the ground potential via the ground resistor (r). Further, at the connection point T1 between the resistance network RG and the ground resistance (r), the reference voltage Vref of the opposite as that given to the resistance network RG is connected via the return resistor R' of the same resistance value as the resistance network RG and the switch S2 in interlocking with the switch S1. Thus, the potential at the connecting point T1 is the same as ground potential and the current flowing to ground GND is absent.

27. 发明专利

JPS5820028A CODE CONVERTER 失效
公开(公告)号：JPS5820028A
公开(公告)日：1983-02-05
申请号：JP11814281
申请日：1981-07-28
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： MATSUMURA TOSHIHIKO , GOTOU KUNIHIKO , IWATA ATSUSHI , KIKUCHI HIROYUKI
IPC分类号： H03M1/74 , H03M1/66 , H03K13/02
摘要： PURPOSE:To obtain a code converter with a low cost, by controlling a switch which switches the connection between the reference potential and the earth potential to be connected to a capacitor array by means of the code of a signal to be a converted. CONSTITUTION:In the case of D/A conversion, the connection between the reference potential V and the earth potential is inverted by actuating switches SWA and SWB by a controlsignal given from a decoder circuit 15 that supplies a digital signal. As a result, the position is inverted between a capacitor Cx connected to the reference potential of a capacitor array 3 and a capacitor Cy connected to the earth potential. Thus the analog voltage VOUT of positive and negative signals can be delivered with the control signal given from the decoder circuit 15. For the A/D conversion, the connection between the reference potential and the earth potential is inverted successively in a comparison mode and by actuating switches SWA' and SWB' with the control signal given from a decoder circuit 16. As a result, the position is inverted between the capacitors Cx and Cy. Thus the positive and negative analog input signals are obtained through the same decoder circuit.

28. 发明专利

JPS5860831A UNLOCKING DETECTING CIRCUIT 失效
公开(公告)号：JPS5860831A
公开(公告)日：1983-04-11
申请号：JP15972981
申请日：1981-10-07
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： IKEZAWA TOSHI , KARIBE HIROHISA , FUKUI HIROKAZU , ITOU AKIHIKO , IWATA ATSUSHI , KIKUCHI HIROYUKI
IPC分类号： H03L7/089 , H03L7/095
摘要： PURPOSE:To decide on a locking or unlocking state by laching the output state of a latch circuit, which is set by the output of an OR circuit and reset by a gate delay circuit, by a clock signal. CONSTITUTION:A phase advance and a phase delay signal outputted from a phase comparator 4 are applied to an OR circuit 11. The output signal of the OR circuit 11 is divided into two; one is applied to a gate delay circuit 12, and the other is applied to the set input of a latch 13. The output signal of the gate delay circuit is applied to the reset input of the latch 13. The output signal of the latch 13 is applied to an input D of a D type flip-flop, and the latch clock of a frequency divider 7 is applied to a clock input to latch the state of the data input at a rise of the clock input. The output signal of the D type flip-flop 14 is used for control over other circuits as a signal for showing the decision result of the locking or unlocking state of a PLL.

29. 发明专利

JPS5820029A ANALOG-TO-DIGITAL CONVERTER 失效
公开(公告)号：JPS5820029A
公开(公告)日：1983-02-05
申请号：JP11814081
申请日：1981-07-28
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： MATSUMURA TOSHIHIKO , FUKUI HIROKAZU , ITOU AKIHIKO , UCHIMURA KUNIHARU , IWATA ATSUSHI
IPC分类号： H03M1/38 , H03M1/80 , H03K13/05
摘要： PURPOSE:To obtain an A/D converter which is free from an error caused by offset voltage, by feeding the sampling value of an analog signal to a voltage follower type comparator and performing the sampling with addition of the offset voltage of the comparator. CONSTITUTION:For an A/D converter containing a D/A converting circuit, a comparator and a sequential comparator, an end of plural capacity elements 22 of the D/A converting circuit to the negative input of a comparator 23. At the same time, the other end of the element 22 is connected to a switch SW24 that switches an input signal Vin between reference potential VR and the earth potential. The positive input of the cmparator 23 is connected to a switch SW25 which performs the switching between the potential VR and the earth potential. Then an output signal is fed back to a negative input via a switch SW21. The SW21 is closed with the SW24 and SW25 connected to the signal Vin and the earth, respectively. Then the SW21 is opened, and the SW24 is earthed. The signal Vin is sampled with the capacity 22, and the polarity of the Vin is decided. According to the positive or negative polarity of the Vin, the SW25 is connected to the potential VR or the earth. Then a part of the SW24 is earthed with the other part connected to the VR. The SW21 is closed and then opened, and the comparator 23 performs a sequential comparison. Thus the offset is eliminated for the A/D conversion.

30. 发明专利

JPS55166324A SWITCHED CAPACITOR FILTER 失效
公开(公告)号：JPS55166324A
公开(公告)日：1980-12-25
申请号：JP7486179
申请日：1979-06-14
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： UENO NORIO , KATOU SEIJI , IWATA ATSUSHI
IPC分类号： G11C27/02 , H03H19/00
摘要： PURPOSE:To secure the fixed output characteristics at all times to the change of the holding time, by providing at least one unit of the switch holding capacitor to the holding time and then the same capacitors in the number of units corresponding to the clock cycle number within the non-holding time to the non-holding time respectively. CONSTITUTION:Switched capacitors CA31, CA32 and CA3 possess the same capacity C, and are charged in accordance with input voltage V1 when connected to the side of the input terminal and then discharge to integrated capacitor CB1 when connected to the side of operational amplifier A1 respectively. Then in the holding time, capacitor CA31 supplies the charge of the save value in the fixed times to capacitor CB1 and with every clock cycle tau=1/fc (fc: clock frequency). On the other hand, capacitors CA32 and CA33 supply the same charge as that in the holding time to capacitor CB1 and every time tau in sequence in the non-holding time. Thus the same charge is always applied to capacitor CB1 via the discharge belonging to one sampling cycle. As a result, the fixed characteristics can always be ensured to the change of the holding time.

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