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    • 21. 发明专利
    • BUFFER MEMORY CONTROL SYSTEM
    • JPS56117400A
    • 1981-09-14
    • JP2086380
    • 1980-02-20
    • FUJITSU LTD
    • ITOU MATAOTSUNODA HARUHIKO
    • G06F11/10G06F12/08G06F12/12G06F12/16
    • PURPOSE:To make the correction of data and tag data without making the constitution complicated and without increasing the buffer access time, by controlling the status of ineffective bit of data at the detection of parity error of data or tag data at buffer access. CONSTITUTION:If the data read out from the data 5 has error, the error register 14 is set with the parity check circuit 10 and the error is set to the instruction unit. Further, the set number indicating the error detecting position is set to the error address register 27 to inhibit the access from the instruction unit, and if the alteration bit in the tag data corresponding to the data of error detection is OFF, the content of the effective address register 1 is corrected with the register 27 to make ON the ineffective bit of the tag data. In case of ON, the data is corrected, the ineffective bit is made ON, and correction is made with shorter access time with a simple constitution through the control based on the parity check only the same as the tag data.
    • 29. 发明专利
    • Method for controlling interface
    • 用于控制界面的方法
    • JPS6159562A
    • 1986-03-27
    • JP18115584
    • 1984-08-30
    • Fujitsu Ltd
    • TSUNODA HARUHIKO
    • G06F13/38G06F11/00G06F13/00G06F13/40
    • G06F13/4072
    • PURPOSE:To prevent a signal not intended by a program from being transmitted to a bus by adding ON of a flag of an interface part to the signal transmissible condition to a bus and turning, further a flag into ON by micro program recog nizing the drive demand. CONSTITUTION:At the time when a hardware recognizes a drive demand, i.e. the output of gates 4, 6 is 1, a gate 9 is opened to give a drive demand to a micro program mu. At this time, a driver DV does not turn ON because a gate 7 does not open, and nothing is transmitted to a bus 8. A driver DV turns ON after a flag 10 is set. At this state, mu acts receiving the drive demand, and a response signal to be transmitted to the bus 8 is set. Consequently, the correct response signal can be transmitted to the bus 8. When a logic device receives data and falls down the drive signal, the output of an OR gate 6 becomes at an L level, the drive DV turns OFF after gates 7, 9 are closed, the response signal and flag 10 are reset after the bus 8 is opened.
    • 目的:为了防止程序不想要的信号通过向总线加上ON将接口部分的标志与信号可传输条件相加,并转向总线,通过微程序进一步标记为ON,记录驱动器 需求。 构成:当硬件识别出驱动器需求时,即门4,6的输出为1时,门9打开以给予微程序mu的驱动要求。 此时,由于门7不打开,驱动器DV不会接通,并且没有任何东西被发送到总线8.驱动器DV在标志10被置位之后变为ON。 在该状态下,mu接受驱动要求,并设定要发送到总线8的响应信号。 因此,可以将正确的响应信号发送到总线8.当逻辑装置接收到数据并降低驱动信号时,或门6的输出变为L电平,驱动器DV在门7,9之后关闭 在总线8断开之后,响应信号和标志10被复位。