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    • 22. 发明专利
    • Manufacture of semiconductor device
    • 半导体器件的制造
    • JPS59205747A
    • 1984-11-21
    • JP8031183
    • 1983-05-09
    • Matsushita Electric Ind Co Ltd
    • KONDOU SHIYUUJIHIRAI MINORUHATADA KENZOU
    • H01L25/00H01L21/3205H01L23/52H01L23/538H01L25/065H01L25/07H01L25/18H01L27/00
    • H01L25/0657H01L23/5385H01L2224/04105H01L2224/20H01L2224/211H01L2225/06524H01L2225/06551H01L2225/06579H01L2924/07802H01L2924/09701H01L2924/00H01L2924/00012
    • PURPOSE:To obtain a device having three-dimensional mounting structure while mutually connecting semiconductor elements easily by loading the semiconductor element on a substrate, mounting an electrode terminal while one end is exposed to the edge section of the circumferential wall of the element, bonding a large number of the substrates with a heat-resisting resin and mutually connecting the exposed electrode terminals. CONSTITUTION:A semiconductor element 17 is loaded on an insulating substrate 22, the edge section of the circumferential wall of the element is surrounded by a heat-resisting resin substrate 19, a side surface thereof has an electrode conductive layer 12 and the surface thereof an electrode conductive layer 20, and the projecting section 20' of the conductive layer 20 is connected to a projecting electrode 18 for the element 17. A plurality of the substrates 22 manufactured in this manner are superposed on a ceramic and glass epoxy resin substrate 23 through spacers 24 in small width, an upper surface is coated with a base body 25, and the substrate 23 and the cover body 25 are clamped by a holding frame body 26 and fixed temporarily. Space formed by the spacers 24 is filled with an insulating adhesive resin 27 such as epoxy and the resin is cured, and the electrode conductive layers 21 exposed to the side surfaces are connected with each other, thus manufacturing a device having three-dimensional structure.
    • 目的:为了获得具有三维安装结构的装置,同时通过将半导体元件加载在基板上而容易地连接半导体元件,在将一端暴露于元件的周壁的边缘部分的同时安装电极端子, 大量的具有耐热树脂的基板并且相互连接暴露的电极端子。 构成:将半导体元件17装载在绝缘基板22上,元件周壁的边缘部分被耐热树脂基板19包围,其侧面具有电极导电层12,其表面为 电极导电层20和导体层20的突出部分20'连接到用于元件17的突出电极18上。以这种方式制造的多个基板22被叠置在陶瓷和玻璃环氧树脂基板23上 间隔物24的宽度小,上表面涂有基体25,基板23和盖体25被保持框体26夹紧并暂时固定。 由间隔物24形成的空间填充有诸如环氧树脂的绝缘粘合剂树脂27,并且树脂固化,并且暴露于侧表面的电极导电层21彼此连接,从而制造具有三维结构的装置。
    • 23. 发明专利
    • Semiconductor device
    • 半导体器件
    • JPS58223366A
    • 1983-12-24
    • JP10721682
    • 1982-06-21
    • Matsushita Electric Ind Co Ltd
    • SHIRAGASAWA TSUYOSHIKONDOU SHIYUUJI
    • G06F11/20H01L21/3205H01L21/82H01L23/52H01L23/525H01L27/10
    • H01L23/5252H01L2924/0002H01L2924/00
    • PURPOSE:To enable to realize a redundant circuit without deteriorating the reliability by a method wherein an oxide film which can be broken down by impressing voltage is provided between two conductive layers. CONSTITUTION:An insulating oxide film 12 and the conductive layer 13 are formed on the surface of a semiconductor substrate 11. An insulation oxide film 14 is provided on the main surface including this layer 13, and an aperture 15 is provided at a part positined above the layer 13 of this film 14. The oxide film 16 which can be broken down by impressing voltage is formed in this aperture 15. Further, the conductive layer 17 is formed at a part of the film 14 including the aperture 15. The film 16 in this constitution can be easily broken down by impressing voltage, e.g. 10V one between the layers 13 and 17. That is, since the change of circuit can be performed without the necessity for passing a large current, or without increasing temperature, a semiconductor device having a redundant circuit of high reliabiity can be realized.
    • 目的:通过在两个导电层之间设置能够通过施加电压而分解的氧化膜的方法,能够实现冗余电路而不劣化可靠性。 构成:在半导体衬底11的表面上形成绝缘氧化膜12和导电层13.在包括该层13的主表面上设置绝缘氧化膜14,并且在上述部分上设置有孔15 该膜14的层13.在该孔15中形成可以通过施加电压而分解的氧化膜16.此外,导电层17形成在包括孔15的膜14的一部分。膜16 在这种结构中,可以通过施加电压容易地分解,例如 也就是说,由于可以在不需要通过大电流或不增加温度的情况下执行电路的改变,所以可以实现具有高可靠性的冗余电路的半导体器件。
    • 24. 发明专利
    • METHOD FOR CONTROLLING COPYING MACHINE
    • JPS58208760A
    • 1983-12-05
    • JP9159282
    • 1982-05-28
    • MATSUSHITA ELECTRIC IND CO LTD
    • OOMURA MORIHARUKONDOU SHIYUUJI
    • G03G21/00G03G15/00
    • PURPOSE:To improve the handling of a copying machine and to prevent the miss of copying, by selecting automatically a paper feeding device only when there is the paper of the previously set up size. CONSTITUTION:The user sets up the number of copies on a display device 2 by numeral keys 1 consisting of 0-9. A COPY key 4 is prepared to copy an original by the prescribed value displayed on the setting display device 2 and is effective only when a READY display 5 is turned on. When the COPY key 4 is depressed, the copying machine starts to operate and the contents of an added number display device 6 is added by ''1'' in every completion of one exposure. When the contents of the display device 6 reaches the value displayed on the display device 2, the copying mode is completed and the machine stops. The paper feeding device selected at present can be switched to another paper feeding device by a cassette selection key 11 and the contents of the newly selected device is displayed on a paper size display device group 12 or a paper feed display device 13.
    • 25. 发明专利
    • Semiconductor device
    • 半导体器件
    • JPS58196030A
    • 1983-11-15
    • JP7895382
    • 1982-05-10
    • Matsushita Electric Ind Co Ltd
    • KONDOU SHIYUUJI
    • H01L21/822H01L21/66H01L27/04
    • H01L22/00
    • PURPOSE:To remove the interference of leak resistance of adjoining lead pins generated due to dew concentration and the like when an inspection is performed by a method wherein a collector terminal having a high rated bias voltage and an emitter terminal having a low rated value are arranged separately. CONSTITUTION:The emitter of transistors Q1-Q4 placed in the package is arranged in lead terminals 1p-4p, a base is arranged in a lead terminal 5p, and a collector is arranged in lead terminals 6p-9p respectively in separate constitution. To be more precise, all terminals adjoining to an emitter terminal of low allowable application bias value are composed of terminals having potential lower than that of equipotential of that of the same terminals, and high potential terminals are arranged separately, thereby enabling to prevent the effect of bias applied to the high potential terminal inflicting on the low potential even when leak resistance is generated between lead terminals.
    • 目的:为了消除通过采用以下方法进行检查而产生的由于露点浓度等产生的相邻引脚的泄漏电阻的干扰:其中布置了具有高额定偏置电压的集电极端子和具有低额定值的发射极端子 分别。 构成:放置在封装中的晶体管Q1-Q4的发射极配置在引线端子1p-4p中,基极配置在引线端子5p中,集电体分别以引导端子6p-9p分别构成。 更准确地说,与允许应用偏差值低的发射极端子相邻的所有端子由具有低于同一端子的等势电位的端子构成,并且高电位端子分开设置,从而能够防止效果 即使在引线端子之间产生泄漏电阻,也施加到施加在低电位上的高电位端子的偏置。
    • 26. 发明专利
    • SEMICONDUCTOR DEVICE
    • JPS58141535A
    • 1983-08-22
    • JP2471982
    • 1982-02-17
    • MATSUSHITA ELECTRIC IND CO LTD
    • SHIRAGASAWA TSUYOSHIKONDOU SHIYUUJI
    • H01L21/31H01L21/60
    • PURPOSE:To prevent corrosion of Al electrodes and Al wiring due to ion and water having entered or penetrated into a mold resin material by providing a protection film to the Al electrode portion. CONSTITUTION:A surface protecting film 5 consisting of a phosphorus glass or nitride film is formed on the main surface of an Al wiring 3 and an Al electrode 4 on an insulating oxide film 2. After die bonding to the die bond land 7 of package, a metal fine lead 8 such as Al or Au is wire-bonded to the Al electrode 4. Then, the surface of Al thin film 6 is oxidized and an alumina layer is thereby formed. As a means of forming an alumina layer, it can be formed efficiently by leaving such Al thin film for several minutes within the gas ambient of fuming nitric acid. The alumina layer is thus formed on the entire part of surface of Al thin film layer except for the joint area with the bonding wire. After the alumina layer is formed, a semiconductor device is resin-molded by the epoxy resin and also sealed and settled.
    • 27. 发明专利
    • SEMICONDUCTOR DEVICE
    • JPS5815263A
    • 1983-01-28
    • JP11396181
    • 1981-07-20
    • MATSUSHITA ELECTRIC IND CO LTD
    • KONDOU SHIYUUJI
    • H01L23/50H01L23/60
    • PURPOSE:To prevent the damage of a circuit element chip associated in a package by the influence of static electricity when the static electricity is applied to the lead terminal of the package. CONSTITUTION:The end of a lead terminal 4 is formed in a structure having a shortcircuit lead 8 at one end of a shortcircuit plate 7. The coupler 9 of the terminal 4 to the plate 7 is formed in a shape such as wedge or conical shape at the end of the terminal 4, and is constructed locally in an ultrafine coupling structure with the plate 7. Accordingly, when several bending forces are applied to the plate 7, the coupler 9 can be simply and readily broken, and the plate 7 and the terminal 8 can be separated. In this manner, since all the lead terminals are connected immediately before use, even if static electricity is applied to the lead terminal during the stock or transportation, all the leads becomes the same voltage. Thus, an accident of damaging the circuit element chip due to the production of potential difference at the chip can be prevented.