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21. 发明专利

JPH04275448A EVALUATION PATTERN FOR SEMICONDUCTOR PROCESS 失效
公开(公告)号：JPH04275448A
公开(公告)日：1992-10-01
申请号：JP3712191
申请日：1991-03-04
申请人： MATSUSHITA ELECTRONICS CORP
发明人： KOIKE NORIO , MAYUMI SHUICHI , UEDA SEIJI
IPC分类号： H01L21/66
摘要： PURPOSE:To evaluate the step coverage of a wiring at a contact hole zone quantitatively and exactly only by electrical measurement. CONSTITUTION:An aluminum wiring 1 having contact holes 2 each of which has short and long sides and is much wider in the long side than the width of the aluminum wiring 1 and continuous in the long side crosses the center of a contact hole 2; therefore, a zone of the aluminum wiring 1 which covers a contact hole 2 is recessed uniformly in width.

22. 发明专利

JPH0322475A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0322475A
公开(公告)日：1991-01-30
申请号：JP15646989
申请日：1989-06-19
申请人： MATSUSHITA ELECTRONICS CORP
发明人： UEDA SEIJI
IPC分类号： H01L27/10 , H01L21/28 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To dispense with takeout of an electrode from a deep contact window by depositing a plug and a storage electrode by the growth of the same N-type polycrystalline silicon film and by lessening a difference in height between them. CONSTITUTION:Windows are made in openings 102 and 103 of a capacitor and a bit-line contact by using a photoresist 101. After interlayer insulation films 7 and 8 are opened, an N-type polycrystalline silicon film 10 to be a lower electrode of the capacitor being a storage electrode is deposited. The window 103 of the contact is filled up with M-type polycrystalline silicon. The N-type polycrystalline silicon film 10 is patterned to form the storage electrode, while the window of the contact is formed in an etched-back shape and left in a self-coordination manner and turns to be a polycrystalline silicon plug. Accordingly, a bit line can be lead out with ease.

23. 发明专利

JPH0322420A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0322420A
公开(公告)日：1991-01-30
申请号：JP15647189
申请日：1989-06-19
申请人： MATSUSHITA ELECTRONICS CORP
发明人： NISHIWAKI TORU , MAYUMI SHUICHI , UEDA SEIJI
IPC分类号： H01L21/28 , H01L21/265 , H01L21/314 , H01L21/316 , H01L21/318 , H01L21/336 , H01L29/43 , H01L29/78
摘要： PURPOSE:To prevent the taking-in of boron to a silicon oxide film, and to obtain low contact resistance by forming the silicon oxide film, implanting B or BF2 ions, annealing the whole in an inert gas atmosphere and shaping a silicon nitride film. CONSTITUTION:A specified LOCOS film 2, a gate oxide film 3 and a polycrystalline silicon gate 4 are formed onto an N-type semiconductor substrate 1. A silicon oxide film 6 is shaped onto the surface of the polycrystalline silicon layer 4 and the surface of the semiconductor substrate 1 through heat treatment in an atmosphere containing oxygen or steam. B or BF2 is implanted, and source-drain diffusion layers 5 are formed through annealing treatment in a nitrogen atmosphere. A silicon nitride film 7 and an inter-layer insulating film 8 are shaped, and contact windows and electrode wirings 11 are formed, thus completing a MOS type semiconductor device. B or BF2 ions are implanted, and the surface of the semiconductor substrate is not oxidized, thus preventing the lowering of the surface impurity-concentration of the source-drain diffusion layers, then acquiring low contact resistance.

24. 发明专利

JPH02281756A COMPOSITION OF ELECTRODE LEADING-OUT SECTION 失效
公开(公告)号：JPH02281756A
公开(公告)日：1990-11-19
申请号：JP10164589
申请日：1989-04-24
申请人： MATSUSHITA ELECTRONICS CORP
发明人： UEDA SEIJI
IPC分类号： H01L23/52 , H01L21/28 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L27/04 , H01L29/41 , H01L29/43
摘要： PURPOSE:To compose an electrode, which maintains the stability of connection and can be formed easily, by exposing an impurity diffusion layer, depositing one or a plurality of conductive films, shaping wiring patterns to the conductive films and leading out the electrode. CONSTITUTION:The sidewall 111 of an inter-layer insulating film 10, the sidewall 112 of a polycrystalline silicon film 8, etc., forming the inwall of a contact hole 11 are oxidized thinly, a silicon dioxide film 13 is shaped, and a silicon nitride film 21 and a polycrystalline silicon film 22 are deposited successively in specified thickness. A source-drain diffusion layer 9a on the bottom of the contact hole 11 is exposed, an aluminum alloy film 12 is evaporated, and an aluminum wiring pattern organizing a bit line, etc., is formed through photoetching and annealing treatment is executed, thus constructing the leading- out section of an electrode. Accordingly, the area of the opening of the contact hole can be expanded substantially, and coatability by the evaporation of an aluminum alloy, etc., is improved, thus allowing the stable leading-out of the electrode.

25. 发明专利

JPH02278763A MEMORY CELL AND ITS FORMATION 失效
公开(公告)号：JPH02278763A
公开(公告)日：1990-11-15
申请号：JP9872789
申请日：1989-04-20
申请人： MATSUSHITA ELECTRONICS CORP
发明人： UEDA SEIJI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To realize a high density of a cell by a method wherein a breakdown strength between cells is constituted independent of a breakdown strength of an N diffusion layer. CONSTITUTION:A switching MOS transistor is constituted on a P-type silicon substrate 1 at the upper part of a sidewall of an island-shaped part composed of silicon. A charge-storage electrode 10a composed of an N-type polycrystalline silicon film 13 is connected to an N diffusion layer 12 formed at the lower part of the switching MOS transistor. It is overlapped with a gate electrode 51 of the switching MOS transistor via interlayer insulating films 17, 20. A plate electrode of the charge-storage electrode 10a is buried inside a groove which has been formed between the island-shaped part and another island-shaped part constituted so as to be adjacent to it. Thereby, a cell capacitance is constituted of a two-layer polycrystalline silicon film; a breakdown strength between cells is not decided by a breakdown strength between N diffusion regions; accordingly, an interval between the cells can be reduced. A DRAM whose cells have been made highly dense can be realized.

26. 发明专利

JPH01157556A FORMATION OF MULTILAYER METAL INTERCONNECTION 失效
公开(公告)号：JPH01157556A
公开(公告)日：1989-06-20
申请号：JP31594587
申请日：1987-12-14
申请人： MATSUSHITA ELECTRONICS CORP
发明人： UEDA SEIJI
IPC分类号： H01L23/522 , H01L21/768
摘要： PURPOSE:To prevent a disconnection by a method wherein a via hole is made wider than a width of a metal wiring part, a connection hole is made large and a stepped part on the bottom of the via hole is removed. CONSTITUTION:A silicon dioxide film 2 is formed on a main face of a P-type silicon substrate 1; an aluminum wiring layer 3 is formed; after that, an interlayer insulating film 4 composed of a silicon dioxide film is deposited. Then, a via hole 12 is made by a photolithographic method. Then, the surface of the exposed aluminum wiring layer 3 is etched by using an etching solution composed mainly of phosphoric acid; the bottom of a groove 5 is made equal to a height of the aluminum wiring layer 3. In succession, an aluminum wiring part 7 is formed on the interlayer insulating film 4. By this setup, it is possible to prevent a metal wiring layer from being disconnected.

27. 发明专利

JPS6430257A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6430257A
公开(公告)日：1989-02-01
申请号：JP18719987
申请日：1987-07-27
申请人： MATSUSHITA ELECTRONICS CORP
发明人： UEDA SEIJI
IPC分类号： H01L21/265 , H01L21/8238 , H01L27/08 , H01L27/092
摘要： PURPOSE:To simplify a manufacturing process by a method wherein each ion- implantation region is determined through two masking processes for the element isolation and the formation of a well region. CONSTITUTION:A silicon dioxide film 2 and a silicon nitride film 3 are formed on an N-type silicon substrate 1, a part of the silicon nitride film 3 is removed which is to be an element isolation region, and then a silicon nitride film 4 is deposited thereon. A photoresist film 5 is formed which has an opening provided for a P well forming region, the silicon nitride film 4 and the silicon dioxide film 2 are subjected to etching through the photoresist film 5 used as a mask, the ion-implantation of boron is performed, and then the photoresist 5 is removed, the implanted boron is driven in for the formation of a P well 6, and thereafter a silicon dioxide film 8a and a diffusion layer 7 are formed through the selective oxidation. The silicon nitride film 4 is removed, the silicon nitride film 3 is patially removed, P ions are implanted through the film 3 left unremoved as a mask, a channel stopper on the P channel side is formed, and then oxidation is partially performed for the formation of an isolation region.

28. 发明专利

JPS63155625A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS63155625A
公开(公告)日：1988-06-28
申请号：JP30207686
申请日：1986-12-18
申请人： MATSUSHITA ELECTRONICS CORP
发明人： UEDA SEIJI
IPC分类号： H01L21/316 , H01L21/31 , H01L21/318
摘要： PURPOSE:To prevent the occurrence of a pinhole and a microcrack at a surface- protective film by a method wherein a phospho-silicate glass film is deposited directly on a wiring part of an aluminum alloy by a vapor growth method and a silicon nitride film is deposited on the coated glass film and an uppermost layer by a plasma-excited vapor growth method. CONSTITUTION:A phospho-silicate glass film 2 and a wiring part 3 which is composed of an aluminum alloy containing 1% silicon are formed on the main face of a silicon substrate 1. Then, the aluminum-alloy wiring part 3 is coated with a phospho-silicate glass film 11 by a vapor growth method. Then, after the phospho-silicate glass film 11 has been deposited, a coating glass film 12 composed mainly of a silanol compound is applied by a spin coating method. Then, a silicon nitride film 13 is deposited by a plasma-excited vapor growth method. Grooves are filled with the coating glass film 12 and the surface becomes flat; as a result, a pinhole at the silicon nitride film and a microcrack at the corner of the grooves are hard to occur.

29. 发明专利

JPS6213062A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6213062A
公开(公告)日：1987-01-21
申请号：JP15163485
申请日：1985-07-10
申请人： MATSUSHITA ELECTRONICS CORP
发明人： UEDA SEIJI
IPC分类号： H01L27/04 , H01L21/822 , H01L29/94
摘要： PURPOSE:To improve the characteristics of a dynamic RAM having a groove- type capacitor and to enhance the density by coating a coating diffusing solution which contains a conductivity imparting impurity on the surface of a substrate which contains the side and bottom of the groove as a diffusion source, thereby uniformly forming an impurity diffused layer. CONSTITUTION:An element separating region 2 and a groove 3 made of silicon dioxide are formed on a P-type silicon substrate 1, a coating diffusing solution in which boron, arsenide, silicide [RnSi(OH)4-n] are dissolved in an organic solvent is rotatably coated to form a coating film 4. A P-type diffused layer 5 and N-type diffused layer 6 are simultaneously formed by diffusing in a nitrogen atmosphere. The film 4 is removed by dipping in a buffer fluoric acid, a silicon dioxide film 7 and a polycrystalline silicon film 8 having a conductivity are accumulated to form an electrode pattern.

30. 发明专利

JPS6213050A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6213050A
公开(公告)日：1987-01-21
申请号：JP15164085
申请日：1985-07-10
申请人： MATSUSHITA ELECTRONICS CORP
发明人： UEDA SEIJI
IPC分类号： H01L21/3205
摘要： PURPOSE:To prevent a cavity from generating in a connecting hole, and to prevent aluminum wirings from being disconnected at the step of the hole and a passivation film from cracking at the top of the hole by burying the recess of the first conductive film of the hole by an insulating film. CONSTITUTION:An N-type diffused layer 12 and a silicon dioxide film 13 are formed on a semiconductor substrate 11 made of P-type silicon. The first conductive film (polycrystalline silicon film) 15 is accumulated on the entire surface, and an insulating film 16 is buried in a recess formed by a hole 14. The burying is executed by coating a film forming material dissolved in an organic solvent with silicide and additive agent, treating at 500-600 deg.C, and removing the oxide film of the excess portion except the recess with fluoric acid solution. Then, an aluminum film 17 is deposited, electrodes and wiring pattern are formed, heat treated to alloy the aluminum and the polycrystalline silicon. The layer 12 is connected by the first conductive layer 15 and the film 17.

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