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21. 发明专利

JPS59117641A Stack length designating system 失效
标题翻译：堆栈长度指定系统
公开(公告)号：JPS59117641A
公开(公告)日：1984-07-07
申请号：JP22626282
申请日：1982-12-24
申请人： Fujitsu Ltd , Hitachi Ltd , Nec Corp , Nippon Telegr & Teleph Corp , Oki Electric Ind Co Ltd
发明人： FURUKAWA KAZUO , YAMADA SHIGEKI , MATSUSHITA MASAYOSHI , SAKATA HIRONOBU , SAKAMOTO YASUHIKO
IPC分类号： G06F9/46 , G06F9/42 , G06F9/48
CPC分类号： G06F9/4426
摘要： PURPOSE:To reduce the burden of a program, by defining a stack length with a data designated by the program at the jump instruction execution and defining a fixed value if the program does not designate with the data and designating the stack length by the program only when it is required. CONSTITUTION:When the control is jumped to a subroutine B by a jump instruction of a main program A, contents of address 400 are read out to a stack length register 2, and a stack length decoder 3 outputs ''no signal'', and contents (64)D of the register 2 are outputted by a selecting circuit 5 and are added to value (700)D of a stack point register 6 by an adding circuit 7, and contents of the register 6 are updated to (764)D. Next, when the control is jumped to a subroutine C, contents (32)D of a fixed data generating circuit 4 are selected in the input of the selecting circuit 5 because contents of address 500 are (0)D, and contents (32)D of the circuit 4 are added to value (764)D of the register 6 by the adding circuit 7, and contents of the register 6 are updated to (796)D.
摘要翻译：目的：为了减轻程序的负担，通过使用程序在跳转指令执行时指定的数据定义堆栈长度，并且如果程序不指定数据并且仅由程序指定堆栈长度，则定义固定值何时需要构成：当通过主程序A的跳转指令将控制跳转到子程序B时，将地址400的内容读出到堆栈长度寄存器2，堆栈长度解码器3输出“无信号”，并且寄存器2的内容（64）D由选择电路5输出，并通过加法电路7与堆栈点寄存器6的值（700）D相加，寄存器6的内容更新为（764）D 。接下来，当控制跳到子程序C时，由于地址500的内容是（0）D，而内容（32）是内容（32），因此在选择电路5的输入中选择固定数据产生电路4的内容（32）D，电路4的D由加法电路7加到寄存器6的值（764）D上，寄存器6的内容被更新为（796）D。

22. 发明专利

JPS56137599A MEMORY UNIT CONTROL SYSTEM 失效
公开(公告)号：JPS56137599A
公开(公告)日：1981-10-27
申请号：JP3888680
申请日：1980-03-28
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： OOKAWA TAKUJI , FURUKAWA KAZUO , FURUKAWA SUMIO , SAITOU MINORU
IPC分类号： G11C29/00 , G11C29/04
摘要： PURPOSE:To enable to change the number of effective information to external device, by providing the selecting means which can select the maximum number of effective information required for information transfer and by replacing the additional memory storing the information of defective element. CONSTITUTION:The defective position of memory element in the memory unit 3 is written in the additional memory 5, and in case of information transfer with the external device 2, based on the information read out from the memory 5, control is made so that the control section 4 avoids the defective part and transfers good part only. In this case, the data selection circuit 6 which can select the maximum effective information number required for the transfer of information, is provided. Thus, even if the number of effective information at the transfer with the external device 2 is changed, it can be coped by only replacing the additional memory 5 simply, without changing the memory unit 3.

23. 发明专利

JPS55150185A INITIALIZATION SYSTEM OF MAGNETIC BUBBLE MEMORY DEVICE 失效
公开(公告)号：JPS55150185A
公开(公告)日：1980-11-21
申请号：JP5578979
申请日：1979-05-09
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： IKUTA AKIRA , FURUKAWA KAZUO , NUNOTANI MASAKATSU , AMANO TSUNEO
IPC分类号： G11C11/14 , G11C19/08
摘要： PURPOSE:To simplify package space by remembering address information by the use of magnetic bubbles of a random minor loop as many as one of powers of ''2'' and then by reading the minor loop again on the basis of read-out minor loop memory information for initialization. CONSTITUTION:Magnetic bubble module 10 remembers address information by using magnetic bubbles of a random minor loop as many as one of powers of ''2''. When a power failure occurs during operation, a bit number corresponding to the address information read out by detector 2 is set to loop counter 6 by way of control circuit 3, register 4 and loop counter control circuit 5 after the electric power source recovers. Comparator 7 compares the contents of register 8, in which the number of bits until an initial bubble is transferred to a fixed value set position via controller 3 is set, to that of counter 6 for initialization. This constitution can simplify the package space and the operation of software.

24. 发明专利

JPS5475947A CONTROL SYSTEM FOR MAGNETIC BUBBLE MEMORY 失效
公开(公告)号：JPS5475947A
公开(公告)日：1979-06-18
申请号：JP14275777
申请日：1977-11-30
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： DEWA HIROSHI , FURUKAWA KAZUO , MISE KEISUKE , NUNOTANI MASAKATSU
IPC分类号： G11C11/14 , G11C19/08
摘要： PURPOSE:To reduce the access time, by adding the rotating magnetic field simultaneously, by giving the address corresponding to the number of a given memory area in one chip of the magnetic bubble memory to one module and the subsequent address to another module. CONSTITUTION:When the instruction from the data channel unit 50 is decoded with the decoder 130 via the buffer register 100 and the command register 120, the rotating magnetic field formation circuits 140 and 145 are started and the transfer of each magnetic bubble in the minor loop in the modules 1 and 2 is started. The addresses 0 to 63 are given to the bubble located at the same bit location to the minor loop, and the addresses 64 to 127 are given to the next bit location passed by a half of the length of other minor loop in the module 2. Further, during the read and write after the bubble information is transferred, the effect due to noise can be prevented so that another information in the same chip can not be transferred to the read and write region, and the continuous address is sequentially processed with a plurality of modules, then the access time can be reduced.

25. 发明专利

JPS5475945A MAGNETIC BUBBLE CONTROLLER 失效
公开(公告)号：JPS5475945A
公开(公告)日：1979-06-18
申请号：JP14275577
申请日：1977-11-30
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： IWAMOTO YOSHIHARU , FURUKAWA KAZUO , MISE KEISUKE , NUNOTANI MASAKATSU
IPC分类号： G11C11/14 , G11C19/08
摘要： PURPOSE:To control the elements different in memory capacity at the same way, by providing the circuit in which the timing operating the transfer gate and sensor of the magnetic bubble memory element is directly given to element and is done delayed by a suitable time. CONSTITUTION:When the samll capacity bubble memory element is connected to the distrubition circuit 57, the selector switch 568 is at ON state. When the output 03 of the address conversion 51 is 1, the transfer timing TRF signal T and the sensor timing S are fed to the memory element 581 as they are. If the output 03 is zero, desired timing is appeared only at the element 582. Next, the switch 568 is opened and it connects the large capacity element. When the output 03 is 1, TRFTo and the sensor timing So are fed to the element 581 or the element 582, and TRTFT1 and the sensor timing S1 are fed to the element 582 or 581. In this case, since the signal T1 and S1 are delayed by a given time with the delay circuits 562 and 564, access time can be made equal even with large capacity and also small capactity.

26. 发明专利

JPS5475940A MEMORY CONTROL SYSTEM 失效
公开(公告)号：JPS5475940A
公开(公告)日：1979-06-18
申请号：JP14276077
申请日：1977-11-30
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： FURUKAWA KAZUO , FURUKAWA SUMIO
IPC分类号： G11C11/14 , G11C19/00 , G11C19/08 , G11C27/04
摘要： PURPOSE:To realize the memory control system easy for constitution, by providing the memory storing the accumulated information for the defective group with the memory group storing the information of non-defective and defective loop group in a plurality of information loops of shift register memories. CONSTITUTION:Corresponding to the additional memories 20 and 21 writhing in ''0'' to the address N if the Nth loop group is good and ''1'' if defective, the memories 160 and 161 which write in the difference between the Nth normal loop group number Nm and N to the address N and store the information of the accumulating number of the defective loop group are provided. At a certain time, the address register 4 is collated with the time counter 3, and even if the transfer display FF7 is turned on, the content of the memory 160 is read out at the accumulating display counter 170, and if it is more than 1, the output of the gate 140 and the defective display signal 13 are 1, and no data transfer is made. When time is advanced and the counter 170 is counter down into 0, the output of the gate 180 is 0, and the output of FF7 is inputted from the gate 8 to the transfer control circuit 9, starting transfer.

27. 发明专利

JPS53129926A MEMORY CONTROL SYSTEM 失效
公开(公告)号：JPS53129926A
公开(公告)日：1978-11-13
申请号：JP4444677
申请日：1977-04-20
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： FURUKAWA KAZUO , FURUKAWA SUMIO
IPC分类号： G06F12/16 , G06F11/20 , G11C11/14 , G11C19/08 , G11C19/28
摘要： PURPOSE:To realize the faulty loop selection memory control system which features the reduced hardware quentity, simplified constitution and furthemore enhanced chip yield, by installing an additional memory which stores the inforamtion indicating whether the information loop is a normal loop or a faulty loop.

28. 发明专利

JPS5485641A MEMORY UNIT 失效
公开(公告)号：JPS5485641A
公开(公告)日：1979-07-07
申请号：JP15289777
申请日：1977-12-21
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： MASUDA TAKESHI , FURUKAWA KAZUO , FURUKAWA SUMIO , AMANO TSUNEO
IPC分类号： G11C11/14 , G06F11/07 , G11C7/00
摘要： PURPOSE:To reduce the capacity of status memory ROM and to enhance the economical property by storing the information showing the defectiveness only for the address containing the defect. CONSTITUTION:The difference point is that the following units are provided: ROM31 which indicates the normal or abnormal loop in the correspondence of each minor loop of the minor loop group at the address (minor loop number) of the unit information in which the defective minor loop exists and also stores the information showing the defective loop group against the minor loop group based on the minor loop numbers; coincidence detector circuit 33 which detects the value of signal output line 32 of the counter which prescribes the rotary magnetic field of the bubble memory chip and displays the minor loop number of the information being read out currently brom the bubble memory as well as the value the output (bit position 2 -2 ) of the address information of the unit information containing the defective loop plus output line 32; and gate 34 which supplies 2 -2 bits of ROM31 to control signal production circuit 24 via coincidence signal 33.

29. 发明专利

JPS5475943A MEMORY CONTROL SYSTEM 失效
公开(公告)号：JPS5475943A
公开(公告)日：1979-06-18
申请号：JP14275377
申请日：1977-11-30
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： MASUDA TAKESHI , FURUKAWA KAZUO , AMANO TSUNEO , FURUKAWA SUMIO
IPC分类号： G11C11/14 , G11C19/08
摘要： PURPOSE:To establish the memory control system high in economy with simplified constitution, by memorizing the specific pattern displaying the end of a given block length of the memory information on the memory loop in shift register to the conditional memory unit in advance. CONSTITUTION:To the condition memory ROM 22 memorizing the propriety of the minor loop of the magnetic bubble memory, the specific pattern displaying the end of one information block is written in advance. The memory information of 10- bit is read out from each chip 6i(i=0 to 9), the AND gate of the selector 8i is controlled with the control signal forming circuit 24, and if the information from ROM 22 detects defective chip, replacement is made to the chip number of NO.8 and 9. Further, the information from ROM 22 generates the defective byte signal 25 and the final byte display signal 26 with the circuit 24 and it is outputted to the upper rank controller, which blocks the transfer operation between the memory unit and the processor.

30. 发明专利

JPS53129931A CONTROL SYSTEM FOR MAGNETIC BUBBLE MEMORY DEVICE 失效
公开(公告)号：JPS53129931A
公开(公告)日：1978-11-13
申请号：JP4444577
申请日：1977-04-20
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： YASUI ISAMU , FURUKAWA KAZUO , AMANO TSUNEO , FURUKAWA SUMIO
IPC分类号： G11C11/14 , G06F12/00 , G11C19/08
摘要： PURPOSE:To realize an address control system of a simple circuit constitution which can decrease the hardware quantity without lowering the performance of the magnetic bubble memory device, by adding only one unit of munormajor address counter MMC.

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