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21. 发明专利

JPS57150199A MEMORY DEVICE 失效
公开(公告)号：JPS57150199A
公开(公告)日：1982-09-16
申请号：JP3533881
申请日：1981-03-13
申请人： HITACHI LTD
发明人： ITOU SATOSHI , FUKUSHI MOTONOBU
IPC分类号： G06F12/16 , G06F11/10
摘要： PURPOSE:To obtain an error detection/correction code memory device which can also detect address failure, without increasing the number of bits of a memory, by relating an address parity code to the production in an error detection and correction code. CONSTITUTION:At write-in, apparently 17-bit information which consists of 16-bit of written-in information and one-bit of address parity bit from a parity generating circuit 1 in response to an address, is applied to an error detection and correction code generating circuit 2, and the 16-bit information and the 6-bit error detection and correction code are written in a memory 3. At readout, the 16-bit information from the memory 3, the 6-bit error detection and correction code and the address parity bit from the circuit 1 are applied to an error detection code check and correction circuit 4, where the 1-bit error corresponding to the information is corrected, the 2-bit error is detected as the error, and the 1-bit error corresponding to the address parity error is detected as the address error, allowing to detect address failure without increasing the number of bits.

22. 发明专利

JPS5729126A Bus control system 失效
标题翻译：总线控制系统
公开(公告)号：JPS5729126A
公开(公告)日：1982-02-17
申请号：JP10392780
申请日：1980-07-29
申请人： Hitachi Ltd
发明人： YAMANOUCHI MAKOTO , HARA TOSHITAKA , ITOU SATOSHI
IPC分类号： G06F9/46 , G06F13/37 , G06F15/78
CPC分类号： G06F13/37
摘要： PURPOSE:To constitute a large-scale system bus easily by providing different request-to-use lines in parallel to adapters connected to a bus in common, and by connecting the adapters in series by a priority discrimination signal line. CONSTITUTION:Between adapters 2-4 and a right-of-using deciding circuit 1, request-to-use lines REQs 0-3 differing in priority level are provided in parallel, and the adapters are connected to them optionally. Those adapters are connected together in series by a priority discrimination signal line PRO. A circuit 1 monitors requests to use the bus from the adapters through the lines REQs 0-3 and, when those requests arrive, selects one request line having top priority to send its level to permit-to-use-bus signal lines ACKs 0 and 1 and ACKSTB. Each adapter, when not sending the request or not having a level corresponding a permit signal, flows a signal PRO to a following adapter, and an adapter having the level corresponding to the permit signal fetches the signal PRO to obtain the right of using the bus, thereby stopping the transmission of the signal PRO to the next stage.
摘要翻译：目的：通过为连接到总线的适配器并联提供不同的请求使用线路，并通过优先级识别信号线串联连接适配器，从而轻松构成大型系统总线。规定：在适配器2-4和使用权决定电路1之间，并行提供与优先级不同的请求使用线REQ 0-3，并且适配器可选地连接到它们。这些适配器通过优先识别信号线PRO串联在一起。电路1监视通过线路REQ 0-3从适配器使用总线的请求，并且当这些请求到达时，选择一个具有最高优先级的请求线将其电平发送到允许使用总线信号线ACK 0和 1和ACKSTB。每个适配器在不发送请求或不具有对应于允许信号的电平的情况下，将信号PRO流向随后的适配器，并且具有与许可信号相对应的电平的适配器提取信号PRO以获得使用总线的权利从而停止将信号PRO传送到下一级。

23. 发明专利

JPS578875A READING DEVICE 失效
公开(公告)号：JPS578875A
公开(公告)日：1982-01-18
申请号：JP8289780
申请日：1980-06-20
申请人： HITACHI LTD
发明人： EJIRI YASUTOMI , ITOU SATOSHI , KUWABARA YOSHINAGA
IPC分类号： G06K17/00 , B41F33/00 , G06K7/00 , G06K9/00
摘要： PURPOSE:To realize numbering print even in the reading mode for a reading device having a numbering mechanism, by erasing the number that is already printed through a print of the specific pattern and a coating of paint. CONSTITUTION:When a toggle switch 17 is switched to the lower side in the case of a rereading, a gate 18b is made enable with a gate 18a desaved respectively. As a result, a number information 14 is supplied to a pattern generating circuit 16b to be combined with an erased pattern 15b given separately. Thus a numbering print pattern 14b is delivered. The pattern 14b is applied to the numbering mechanism part, and the number 12 printed at the first reading is erased by the pattern of the equal number to give a new print of number 12' at the back of the number 12.

24. 发明专利

JPS5525805A SERVO CIRCUIT OF VIDEO TAPE RECORDER 失效
公开(公告)号：JPS5525805A
公开(公告)日：1980-02-23
申请号：JP9622078
申请日：1978-08-09
申请人： HITACHI LTD
发明人： KOBORI YASUNORI , ITOU SATOSHI , TOKUNAGA YOUICHI , TEJIMA TSUNEHIKO
IPC分类号： H04N5/7826 , G11B5/588 , G11B15/18 , G11B15/467 , G11B15/473 , G11B15/60
摘要： PURPOSE:To obtain a VTR servo circuit which features a high resistance to the tape fluctuation and excellent interchangeability by varying the recording phase of the control pulse showing the recording phase of the video signal in accordance with switching of the tape speed. CONSTITUTION:Division mono-multi 12 divides vertical synchronous signal 11 to obtain division output 13. Output 13 receives the phase delay by delay mono-multi 23 to be turned to delay output 24. Output 24 is supplied to switch 25 along with output 13. Output 24 and 13 are selected at the SP time and the LP time each and then supplied to control head 15 via recording amplifier 14. In other words, the phase of control pulse 10' is delayed largely compared with control pulse 10 via control head 15 at mono-multi 23, and pulse 10' is recorded to track 9 on the tape.

25. 发明专利

JPS54162517A PULSE GENERATING CIRCUIT FOR SERVO CIRCUIT OF HOME VTR 失效
公开(公告)号：JPS54162517A
公开(公告)日：1979-12-24
申请号：JP7091678
申请日：1978-06-14
申请人： HITACHI LTD
发明人： KOBORI YASUNORI , ITOU SATOSHI , SHIBATA AKIRA
IPC分类号： H04N5/7826 , G11B15/46 , G11B15/467 , H04N5/78
摘要： PURPOSE:To readily generate two pulse widths and achieve the reduction of the number of terminals of ICs by opening and closing only one of NAND gates by a switching singnal. CONSTITUTION:Where no trigger signal 26 is inputted, the output 29 is level ''L'' and NAND gates 35, 36 are settled in the state of close and open, respectively, but when the signal 26 is inputted, FFs 30 thru 34 are all reset and the Q outputs of the respective FFs become ''L''. The output 29 then becomes ''H''. Because of this, the gates 35, 36 invert to open and close, respectively, then the clock signal 23 inputs to the T input of the FF 30 which in turn starts frequency division. As the frequency division progresses and when all the NAND gates 37 become ''H'', the output 29 returns to ''L'' and the gate 35 closes to stop the frequency division, thus waiting for the input of the signal 26. Hence, if the dividing frequencies are determined by the FFs 30, 33, 34 by making the switching signal 28 ''L'' and closing the gate 38 at the recording and by the FFs 30, 33, 34 and 32 by reversing the conditions from the above at the reproducing, the arbitrary two pulse widths may be readily generated.

26. 发明专利

JPS5245211A DEVICE FOR CORRECTING SIGNAL PHASE FLUCTUATION 失效
公开(公告)号：JPS5245211A
公开(公告)日：1977-04-09
申请号：JP12057175
申请日：1975-10-08
申请人： HITACHI LTD
发明人： YUMITE YASUSHI , TAKAMIYA MASASHI , ITOU SATOSHI
IPC分类号： H04N5/12 , H04N5/95 , H04N5/956
摘要： PURPOSE:To utilize the correcting device to video player for domestic use by correcting a phase fluctuation by using the simple component of synchronous coupling controller composed of synchronous/clock coupling oscillator and read clock generator.

27. 发明专利

JPS51111310A CASSETTE TAPE RECORDER 失效
公开(公告)号：JPS51111310A
公开(公告)日：1976-10-01
申请号：JP3561175
申请日：1975-03-26
申请人： HITACHI LTD
发明人： SATOU KATSUYA , WATANABE YASUO , ITOU SATOSHI
IPC分类号： G11B15/675 , G11B15/02 , G11B15/10 , G11B15/18 , G11B15/66
摘要： PURPOSE:An easy pausing and ejecting of the cassuette with a push button switch.

28. 发明专利

JPS60246489A OPTICAL CHARACTER READING METHOD 失效
公开(公告)号：JPS60246489A
公开(公告)日：1985-12-06
申请号：JP890585
申请日：1985-01-21
申请人： HITACHI LTD
发明人： HANANOI TOSHIHIRO , ITOU SATOSHI , KOMATSU HITOSHI
IPC分类号： G06K9/32 , G06K9/20 , G06T1/00
摘要： PURPOSE:To generate no read error even if a business form expands and contracts by a variation of temperature and humidity, by providing a detecting means of a position of the business form. CONSTITUTION:When running of a business form 1 is started, a scanning line 7 is projected onto a semiconductor CCD sensor 19. A binary-coding circuit 20 converts an analog data obtained by the CCD sensor 19 to a digital data and stores it in a memory 21. Also, a length of the business form 1 is forecast and programmed in advance, but its actual length is varied in accordance with a variation of temperature and humidity. Therefore, a business form detector 30 is provided, an actual length of the business form 1 is measured based on the time when the business form 1 passes through the business form detector 30, and the length programmedin advance is corrected.

29. 发明专利

JPS60127876A PICTURE INFORMATION COMPRESSING SYSTEM 失效
公开(公告)号：JPS60127876A
公开(公告)日：1985-07-08
申请号：JP23579983
申请日：1983-12-14
申请人： HITACHI LTD
发明人： HIROSE TSUNEO , HANANOI TOSHIHIRO , ITOU SATOSHI , MICHINO MASAO , KURINO KIYOMICHI
IPC分类号： H04N1/413 , H04N1/415
摘要： PURPOSE:To simplify the coding and decoding processing and also to save the capacity of a pattern storage memory by storing a flag bit representing whether or not a word data is stored in a memory to the memory. CONSTITUTION:A paper feed mechanism 9 carries a paper slip 1 by the command of a processor 6. The picture data on the carried paper slip 1 is subjected to photoelectric conversion by sensor 2 and binary-coded at a binary coding circuit 3, then subject to data compression by a coding circuit 4 and the result is stored in a memory 5. The processor 6 applies sequentially decoding to the picture data stored in the memory 5, extracts the character part, processes recognition and displays the result of recognition to a display device 7 or outputs it to an output device 8.

30. 发明专利

JPS60103427A OPTICAL READER 失效
公开(公告)号：JPS60103427A
公开(公告)日：1985-06-07
申请号：JP21129283
申请日：1983-11-10
申请人： HITACHI LTD
发明人： MINAMOTO HIROMITSU , HANANOI TOSHIHIRO , ITOU SATOSHI , HIROSE TSUNEO
IPC分类号： G06K7/016 , G06F3/00 , G06F3/02 , G06F3/06 , G06K9/00 , G06K9/20 , G06K9/62 , G06T1/00
摘要： PURPOSE:To attain connection of an optical reader to a device for data input in place of a keyboard by obtaining the coincidence between the data style delivered from the optical reader and the data style delivered from the keyboard. CONSTITUTION:An interface part 15 of an optical reader recognizes a separated character through a recognizing part 14 and latches the character code by a data latch 15B to deliver the code to a host device in the form of data. At the same time, the part 15 functions to deliver a line feed code when the set number of read digits for each line reaches the set value. The number of digits for each line is preset to a column counter 15C by a switch 16. The counter 15C is counted up every time a character is sent from the part 14 and then cleared when the count value reaches a preset level. At the same time, a signal is delivered to a timing control 15A. When receiving the signal, the control 15A sends out the input character data and then delivers a line feed code through a line feed code generating part 15E.

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