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21. 发明专利

JPS62109176A CONTROL SYSTEM FOR TRANSFER ADDRESS OF PICTURE MEMORY 失效
公开(公告)号：JPS62109176A
公开(公告)日：1987-05-20
申请号：JP25016185
申请日：1985-11-07
申请人： FUJITSU LTD
发明人： YOKOMIZO SHINICHI
IPC分类号： G06T3/00
摘要： PURPOSE:To quickly produce an enlarged transfer address by securing such a mechanism where the transfer is carried out just by designating the area ranges of both transferers and transferees to a DMA controller through a processor. CONSTITUTION:The desired value is set to all transfer address counters as well as each register of a DMA controller 3' of a processor and a transfer processing is started. The transfer start address is stored (means a) in a start point address register and selected (means b). Then the addresses are produced (means c) in the number equal to the magnification ratio of an axis X and the shift amounts are added (means d) to these addresses. Then those addresses are transmitted (means g) from an address bus. This transmission is repeated in the frequency equivalent to the number of block addresses. Thus the transfer is through with the X axis addresses of the 1st column. While the start point addresses of the X axis address train are selected (means f) in the number equal to the magnification ratio of an axis Y. The X axis addresses are transferred successively. A jump amount is added (means e) to the start point address of the relevant column and the start point address of the next X axis address train is produced. This processing is repeated and all transfer address counters transmit the transfer end signals.

22. 发明专利

JPS59124399A Voice recognition equipment 失效
公开(公告)号：JPS59124399A
公开(公告)日：1984-07-18
申请号：JP23408582
申请日：1982-12-30
申请人： Fujitsu Ltd
发明人： USAMI RIYUUICHI , MATSUMOTO MASACHIKA , YOKOMIZO SHINICHI , ARAYA OSAMU , ANDOU SABUROU
IPC分类号： G10L11/00 , G10L15/20 , G10L15/28 , G10L21/02

23. 发明专利

JPS59116799A Dictionary checking system for voice recognition equipment 失效
标题翻译：语音识别设备词典检查系统
公开(公告)号：JPS59116799A
公开(公告)日：1984-07-05
申请号：JP23138882
申请日：1982-12-24
申请人： Fujitsu Ltd
发明人： MATSUMOTO MASACHIKA , ANDOU SABUROU , ARAYA OSAMU , USAMI RIYUUICHI , YOKOMIZO SHINICHI
IPC分类号： G10L11/00 , G10L15/06

24. 发明专利

JPS5977499A Voice recognition equipment 失效
公开(公告)号：JPS5977499A
公开(公告)日：1984-05-02
申请号：JP18791682
申请日：1982-10-26
申请人： Fujitsu Ltd
发明人： ANDOU SABUROU , YOKOMIZO SHINICHI , MATSUMOTO MASACHIKA , ARAYA OSAMU , USAMI RIYUUICHI
IPC分类号： G10L11/00 , G10L15/06 , G10L15/28

25. 发明专利

JPS592098A Voice recognition system 失效
公开(公告)号：JPS592098A
公开(公告)日：1984-01-07
申请号：JP11118682
申请日：1982-06-28
申请人： Fujitsu Ltd
发明人： YOKOMIZO SHINICHI , ANDOU SABUROU , ARAYA OSAMU , USAMI RIYUUICHI , MATSUMOTO MASACHIKA
IPC分类号： G10L11/00 , G10L15/00 , G10L15/28

26. 发明专利

JPS58169616A DMA TRANSFER SYSTEM 失效
公开(公告)号：JPS58169616A
公开(公告)日：1983-10-06
申请号：JP5311082
申请日：1982-03-31
申请人： FUJITSU LTD
发明人： MATSUMOTO MASACHIKA , ARAYA OSAMU , ANDOU SABUROU , YOKOMIZO SHINICHI
IPC分类号： G06F13/28 , G06F3/00
摘要： PURPOSE:To incorporate a storage device of a large capacity exceeding an address space to an I/O device, by gating a memory selection signal with the information that discriminated the contents of a memory selecting register circuit which is controlled by a CPU. CONSTITUTION:Memory selecting register circuits 301, 602 and 702 which can be controlled by a microprocessor unit MPU10 are provided into a main memory MEM30, an input/output device I/OA60 and I/OB70 respectively. The contents of these register circuits are discriminated by decoding circuits 302, 603 and 703 respectively. Then memory selection signals 304, 605 and 705 are gated by gate circuits 303, 604 and 704 with the outputs of above-mentioned discrimination. The storage devices 305, 606 and 706 of the MEM30, I/OA and I/OB respectively are selected by the contents of registers 301, 602 and 702 as well as the address signal on a common bus 20.

27. 发明专利

JPS5733495A Error correcting system 失效
标题翻译：错误校正系统
公开(公告)号：JPS5733495A
公开(公告)日：1982-02-23
申请号：JP10588880
申请日：1980-07-31
申请人： Fujitsu Ltd
发明人： YOKOMIZO SHINICHI
IPC分类号： G06F12/16 , G06F11/00 , G11C11/401 , G11C29/00 , G11C29/42
CPC分类号： G06F11/00
摘要： PURPOSE:To prevent the lowering of the information process efficiency, by correcting the error detected during the reading in the refresh mode after detection of the error. CONSTITUTION:If an error is caused from a storage device 1 and at an output 18, the output 21 of an error detecting circuit 2 sends thd data for which the error is corrected to a processor in the form of a read data RD. In that case, an error detection signal 22 is set to an error address register 3 along with the output 41 of an error register 4. The output 21 of the circuit 2 after correction of the error is set to a data register 5. The signal 22 is supplied also to a refresh address counter 16. In the refresh mode, the output 111 of an OR circuit 11 is supplied to the device 1 in the form of a writing instruction by the output 101 of an AND circuit 10. Thus the device 1 carries out a writing action to write the correct data to the address that had an error during the reading in place of a refresh action.
摘要翻译：目的：为了防止信息处理效率的降低，通过在检测到错误之后更正刷新模式下读取期间检测到的错误。构成：如果从存储设备1和输出18引起错误，则错误检测电路2的输出21以读取数据RD的形式向处理器发送纠错错误的数据。在这种情况下，错误检测信号22与错误寄存器4的输出41一起设置在错误地址寄存器3中。校正错误后的电路2的输出21被设置为数据寄存器5。 22也被提供给刷新地址计数器16.在刷新模式中，OR电路11的输出111以AND电路10的输出101以写入指令的形式提供给器件1.因此，器件 1执行写入操作以将正确的数据写入读取期间具有错误的地址以代替刷新动作。

28. 发明专利

JPS5619126A CLOCK CONTROL SYSTEM 失效
公开(公告)号：JPS5619126A
公开(公告)日：1981-02-23
申请号：JP9532579
申请日：1979-07-26
申请人： FUJITSU LTD
发明人： YOKOMIZO SHINICHI
IPC分类号： G06F1/04
摘要： PURPOSE:To simplify the unit, by counting the start signal after generating the start signal from the access source, delivering the start signal counted at manual clock to accessed source and deleting the output data register of accessed source. CONSTITUTION:In case of manual clock providing the access source 7 and accessed source 8 and operating both sources 7, 8 synchronizingly, MEM, GO signal is held at the shift register 2. Further, immediately before the clock CLK2 from the clock delay circuit 3 requiring the read data at the control unit side is a given value, the specified value of the clock CLK1 from the oscillator 6 is fed to the access selection circuit 5 and delivered to the memory unit MEM of the accessed source 8 via the circuit 5. After that, after inputting the read data to the data register 4 of the access source 7, the data are sampled with the clock CLK2 through the circuit 3 and the switching between the manual cycle and the normal cycle is made with a simple circuit constitution.

29. 发明专利

JPH049895A IMAGE ROTATION SYSTEM 失效
公开(公告)号：JPH049895A
公开(公告)日：1992-01-14
申请号：JP11054390
申请日：1990-04-27
申请人： FUJITSU LTD
发明人： YOKOMIZO SHINICHI
IPC分类号： G09G3/36 , G09G1/04 , G09G3/04 , G09G3/20 , G09G5/00
摘要： PURPOSE:To rotate the display direction of an image through electric operation by providing a means which switching a horizontal scanning signal from a horizontal scanning means to a vertical scanning means and inverts and switches a vertical scanning signal from a vertical deflecting means to the horizontal scanning means. CONSTITUTION:When a lateral display image is converted into a longitudinal display image, the horizontal signal switching means 14 receives a rotation control signal from a control means to switch the horizontal scanning signal generated by a horizontal scanning signal generating means 15 from the horizontal scanning means 12 to the vertical scanning means 13. The vertical scanning signal generated by a vertical scanning signal generating means 16, on the other hand, is inverted and switched from the vertical scanning means 13 to the horizontal scanning means 12. An image signal generating means 17 generates an image signal of English characters B in synchronism with the horizontal synchronizing signal and vertical synchronizing signal and supplies it to a display unit 11. Thus, the rotation of the display image displayed on a display device is controlled through the fully electric signal switching operation.

30. 发明专利

JPS6473447A SYSTEM FOR CONTROLLING LOW ORDER DEVICE 失效
公开(公告)号：JPS6473447A
公开(公告)日：1989-03-17
申请号：JP22976287
申请日：1987-09-16
申请人： FUJITSU LTD
发明人： INESHIMA SHINJI , KAGEYAMA MASAHISA , OI YASUSHI , YOKOMIZO SHINICHI , TAKESHITA JUNKO
IPC分类号： G06F13/12 , G06F13/24 , G06F13/36 , G06F15/16 , G06F15/173 , G06F15/177
摘要： PURPOSE:To speed up an interrupting processing without imposing a big burden on a low-order central processor by providing a signal line for transmitting an interrupting signal from a low-order device to the low-order central processor to a bus adapter part between the low-order device and the bus adapter part. CONSTITUTION:The signal line 7 for transmitting the interrupting signal transmitted from the low-order device 6 to the low-order central processor 5 to the bus adapter part 3 between the low-order device 6 and the bus adapter part 3. Consequently, the interrupting signal from the low-order device 6 is appropriately processed by the command of the high-order central processor 1 and the like according to whether the high-order central processor 1 or the low-order central processor 5 has instructed of starting even if the low-order central processor 5 does not judge the device which has instructed of starting. Thus, the interrupting processing can be executed without imposing the big burden on the low-order central processor 5.

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