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21. 发明专利

JPS56147223A ADDRESS CHANNEL SETTING SYSTEM 失效
公开(公告)号：JPS56147223A
公开(公告)日：1981-11-16
申请号：JP5144080
申请日：1980-04-18
申请人： FUJITSU LTD
发明人： SHIBATA HIROKI , NAKASHIMA TOSHIKI , DOI YASUO , SAWAI TOSHIO
IPC分类号： G06F11/20 , G06F13/00 , G06F15/16
摘要： PURPOSE:To facilitate the address channel setting work, by providing a nonvolatile memory in one stand-by data transferring device to which K sets of address channels are assigned and by holding address channel information corresponding to K sets of machines in use. CONSTITUTION:The stand-by data transfer device is provided with address channel storing memory EROM20 correspondingly to K sets of data transferring devices in use, and address channel information assigned to the system is written preliminarily. EROM20 is provided with memory address forming circuit 21 and memory reading circuit 22 peripherally. The stand-by data transferring device converts switching informaton from stand-by channel designating circuit 7 to a memory address of EROM20 and reads out designated address channel information and transmits it to address deciding circuit 15. Circuit 15 compares address channel information transmitted from the processing device with information read out from EROM20; and if they coincide with each other, the address coincidence signal is returned, and thus, the processing device and the stand-by device are connected logically.

22. 发明专利

JPS56127230A CONNECTING SYSTEM OF INFORMATION PROCESSING PART 失效
公开(公告)号：JPS56127230A
公开(公告)日：1981-10-05
申请号：JP2993280
申请日：1980-03-10
申请人： FUJITSU LTD
发明人： NAKASHIMA TOSHIKI , SHIBATA HIROKI , DOI YASUO
IPC分类号： G06F13/28
摘要： PURPOSE:To minimize the effect caused by fault of a housing and then increase the transfer speed for a connecting system of the infomation processing part contaning a cycle steal transfer controlling part, by connecting the channels to the cycle steal transfer control part. CONSTITUTION:The memory controller 20 selects and gives a permission to the request to receive an access in case the cycle steal transfer controlling parts 21-23 have access requests to the main memory 1. The controlling part 21 transmits the memory access, if given to the memory 1 from the channels 5 and 6, to the controller 20 and at the same time holds it in the buffer 21-1. In the same way, the channels 7-8 plus 9-10 provided at the housings 12 and 13 are connected to the controlling parts 22 and 23 via the cables 24 and 25. Thus the access requests given to the memory 1 from the channels 7-8 and 9-10 to the controller 20. It is possible to connect the channels in parallel to the memory controller in the number equivalent to an increment of the cycle steal transfer controlling parts. As a result, the transfer line can be shortened.

23. 发明专利

JPS5673950A DETECTION SYSTEM FOR COMMUNICATION SPEED OR THE LIKE 失效
公开(公告)号：JPS5673950A
公开(公告)日：1981-06-19
申请号：JP15029579
申请日：1979-11-20
申请人： FUJITSU LTD
发明人： DOI YASUO , ODAKAWA TOSHIYUKI
IPC分类号： H04L25/02 , H04L29/04
摘要： PURPOSE:To constitute the communication controller with less hardware, by discriminating the communication speed through the reception of specific pattern information ahead the start of data communication. CONSTITUTION:When specific data pattern is incoming to a reception data line 9, the count of measuring counter 2 is started for a given time, to advance a sign change counter 1. When a counter 2 counts a given value for a given time, a stop signal is transmitted to the sign change counter 1 and a discrimination circuit 3. The discrimination circuit 3 forms and outputs the speed detection signal based on the count value of the sign change counter 1. Thus, without providing a special hardware with the communication controller, the detection of communication speed can be made.

24. 发明专利

JPS5533304A CIRCUIT SCAN SYSTEM 失效
公开(公告)号：JPS5533304A
公开(公告)日：1980-03-08
申请号：JP10481878
申请日：1978-08-30
申请人： FUJITSU LTD
发明人： DOI YASUO , NAKAMURA TAKASHI , OGAWA YOSHIHISA , ODAKAWA TOSHIYUKI
IPC分类号： H04L29/04 , G06F13/00 , G06F13/22
摘要： PURPOSE:To secure a circuit scan system which is highly efficient and in accordance with the system by transmitting the scan signals is sequence to the next circuit correspondence parts in case no process request is given. CONSTITUTION:Circuit common control part 1 transmits scan signal A from circuit correspondence parts 2a-2n at the process request acceptable time and in fixed cycle. Part 2a, for example, which received signal A transmits signal A directly to the next circuit correspondence part via gate B in case the FFC memorizing the presence or absence of the process request is off, and stops the transmission of signal A in case the FFC is on to transmit the circuit number to transmission circuit 5a via bus line D connecting all circuit correspondence parts in the wired off-logic. At the same time, control part 1 decides the absence or presence of the flyback line of signal A after transmission of signal A and after a fixed time decided by the total delay time of gate B and wiring lengths, and then decides that the process request is not held at all parts 2a-2n in case flyback line A exists. While the fact that the process request is given from the circuit of line D in case no line A exists.

25. 发明专利

JPS52104005A CIRCUIT CHANGEOVER DEVICE WHICH POSSESSES ROOPBACK FUNCTION 失效
公开(公告)号：JPS52104005A
公开(公告)日：1977-09-01
申请号：JP2091576
申请日：1976-02-27
申请人： FUJITSU LTD
发明人： SHIBUKAWA NOBUO , DOI YASUO , SATOU MIKIO
IPC分类号： H04L1/22 , G06F11/20 , G06F11/22 , G06F13/00 , H04L1/24 , H04L29/14
摘要： PURPOSE:To simplify an interactive test by means of using roopback connecting device in a data communication system.

26. 发明专利

JPS5131142A 失效
公开(公告)号：JPS5131142A
公开(公告)日：1976-03-17
申请号：JP10346674
申请日：1974-09-10
申请人： FUJITSU LTD
发明人： DOI YASUO , NAKAMURA TAKASHI
IPC分类号： H04L29/04 , G06F3/00 , G06F13/00

27. 发明专利

JPS6461831A TRANSFER SYSTEM FOR TRACE INFORMATION 失效
公开(公告)号：JPS6461831A
公开(公告)日：1989-03-08
申请号：JP21891087
申请日：1987-09-01
申请人： FUJITSU LTD
发明人： NISHIOKA JUNJI , DOI YASUO , SHIBATA HIROKI
IPC分类号： G06F11/34
摘要： PURPOSE:To reduce the load of a processor and to improve the processing efficiency of a transfer system for trace information, by producing a request command for transfer of the trace information to a processing part when a service processor collects the trace information. CONSTITUTION:When a service processor 1 collectes the trace information within a trace area 6 of a circuit control part 5, the processor 1 produces a request command for transfer of the trace information to a processing part 4. Receiving this request, the part 4 sends a trace information transfer command to the part 5. The part 5 stores one block of the designated area 6 into a specific area for trace information storage 9 of a buffer memory part 7 based a head address. Thus the trace information on the part 5 desired by the processor 1 is stored in the area 9 of the part 7. Then these information are collected by the processor 1 and processed.

28. 发明专利

JPS6159516A Timer device 失效
标题翻译：定时器设备
公开(公告)号：JPS6159516A
公开(公告)日：1986-03-27
申请号：JP18120784
申请日：1984-08-30
申请人： Fujitsu Ltd , Hitachi Ltd , Nec Corp , Nippon Telegr & Teleph Corp
发明人： NAKAJIMA TOSHIKI , DOI YASUO , SHOJI TOSHIO , IKEDA YOSHINOBU , MAKIURA YASUHIKO
IPC分类号： G06F1/14 , G04F3/00 , G06F1/04
摘要： PURPOSE: To use plural controllers in common and to set a lot of kinds of timers at the same time by providing a common timer control section to the plural controllers to connect it to them.
CONSTITUTION: A timer control section TMC5 is a common timer control section connected to CPU1, 2 via a common bus 6 and the timer setting processing and timer ineffective processing are executed in response to a command of the CPUs. Further, timer renewing processing is executed independently with the CPU at a prescribed period and when time-out of a set timer is detected, the CPU1 or 2 is informed through interruption. That is, when a program realized by a CPU starts another program run on the other CPU after a prescribed time. the timer is set to cause interruption in the other CPU after a prescribed time. Thus. the plural CPUs are used in common and a lot of kinds of timers are set at the same time.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：为了同时使用多个控制器并通过向多个控制器提供公共定时器控制部分来连接它们，同时设置许多种类的定时器。构成：定时器控制部分TMC5是通过公共总线6连接到CPU1,2的公共定时器控制部分，并且响应于CPU的命令执行定时器设置处理和定时器无效处理。此外，CPU在规定的时间内独立执行定时更新处理，并且当检测到设定的定时器超时时，通过中断通知CPU1或2。也就是说，当由CPU实现的程序在规定的时间之后启动在另一个CPU上运行的另一程序。定时器被设定为在规定的时间后引起其他CPU的中断。从而。多个CPU被共同使用，并且同时设置了许多种类的定时器。

29. 发明专利

JPS60243743A MULTIPLEX MICROPROGRAM CONTROL SYSTEM 失效
公开(公告)号：JPS60243743A
公开(公告)日：1985-12-03
申请号：JP9867884
申请日：1984-05-18
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： TANIGAKI HIROSHI , MARUYAMA MASATO , IKEDA YOSHINOBU , DOI YASUO
IPC分类号： G06F9/26 , G06F9/22 , G06F9/28
摘要： PURPOSE:To reduce the necessary capacity of a control memory without reducing the processing efficiency of a multiplex microprogram by forming a control memory to be used by respective microprograms in common. CONSTITUTION:Microprogram control means 2-5 are constituted of control memories 10-13 and control parts 20-23 respectively. In addition to these control memories 10-13, a control memory 14 is independently formed in a device 1 and a microprogram in the control memory 14 can be read out by respective microprogram control means 2-5 through a line 34. For instance, the control memories 10-13 are constituted by rapid IC memories having small capacity to store programs having high using frequency. On the other hand, the memory 14 is constituted of a slow memory having large capacity to store a program having low using frequency.

30. 发明专利

JPS60186939A TIMER MECHANISM 失效
公开(公告)号：JPS60186939A
公开(公告)日：1985-09-24
申请号：JP4271584
申请日：1984-03-06
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： NAKAJIMA TOSHIKI , DOI YASUO , SHIYOUJI TOSHIO
IPC分类号： G06F9/48 , G06F1/14 , G06F9/30 , G06F9/46 , G06F13/00 , G06F15/00
摘要： PURPOSE:To prevent the concentration of processing and a malfunction due to said concentration with a timer mechanism, by having the timer replacement processing of just one time which is started in case plural interval timers have time-out at a time. CONSTITUTION:An interval timer circuit 12 of a timer control part TMC5 produces reference signals synchronous with 10ms, 1s and 1min respectively. The interval timers of 10ms and 1s have time-out, and Q1 and Q2 output signals of an REG1 are set at ''1''. Under such conditions, the TMRNG signal and the Q1 output signal of a DEC15 are set at ''1''. Therefore the output signal of an AND gate G4 is set at ''1'' and effective to a timer control word TCW. This shows that an interval timer has time-out. In this case, the TCWs of a time range ''01'' (10ms) or ''10'' (1s) within the TMC5 are regarded as the sujects for timer replacement. Then -1 is fed to the timer value.

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