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21. 发明专利

JP2006258941A Automatic focusing system using pre-gamma correction 审中-公开
标题翻译：自动聚焦系统使用前置伽马校正
公开(公告)号：JP2006258941A
公开(公告)日：2006-09-28
申请号：JP2005073338
申请日：2005-03-15
申请人： Winbond Electron Corp , ウインボンドエレクトロニクスコーポレイションWinbond Electronics Corp.
发明人： MATSUMOTO KAZUYA
IPC分类号： G02B7/28 , G03B13/36 , H04N5/232
摘要： PROBLEM TO BE SOLVED: To provide an automatic focusing system in which precision in automatic focusing is greatly improved and the processing speed of the automatic focusing is greatly increased.
SOLUTION: After having beforehand completed a prescribed function type automatic focusing gamma correction (a pre-gamma correction) for the pixel signals extracted from a prescribed region of an image pickup device, a spatial filtering processing and a weighted integral processing are performed for the automatic focusing.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供自动聚焦精度大大提高并且自动聚焦的处理速度大大增加的自动聚焦系统。解决方案：在从图像拾取装置的规定区域中提取的像素信号预先完成了规定的功能类型自动聚焦伽马校正（前伽马校正）之后，执行空间滤波处理和加权积分处理用于自动对焦。版权所有（C）2006，JPO＆NCIPI

22. 发明专利

JP2006134401A Low power consumption storage apparatus 审中-公开
标题翻译：低功耗存储设备
公开(公告)号：JP2006134401A
公开(公告)日：2006-05-25
申请号：JP2004320693
申请日：2004-11-04
申请人： Winbond Electron Corp , ウインボンドエレクトロニクスコーポレイションWinbond Electronics Corp.
发明人： LIN YU-CHANG , WU MING-CHUN
IPC分类号： G11C11/409 , G11C11/407
摘要： PROBLEM TO BE SOLVED: To provide a storage apparatus in which power consumption is reduced largely.
SOLUTION: This apparatus is a storage apparatus to which external power source voltage is supplied from an external power source, and is a memory cell array including a plurality of memory cells prescribed by a plurality of bit lines and a plurality of word lines, each memory cell has a memory cell array corresponding to the prescribed bit line and the prescribed word line, an equalizing circuit equalizing the plurality of bit lines in a pre-charge process, a multiplex circuit selecting at least one bit line out of the plurality of bit lines, a plurality of word line control circuits controlling selection of one word line out of the plurality of word lines, a first voltage generator supplying first power source voltage to the plurality of word line control circuits, and a second voltage generator supplying second power source voltage being lower than the first power source voltage to the equalizing circuit and the multiplex circuit.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种功耗大大降低的存储装置。解决方案：该装置是从外部电源提供外部电源电压的存储装置，是包括由多个位线和多个字线规定的多个存储单元的存储单元阵列每个存储单元具有对应于规定位线和规定字线的存储单元阵列，在预充电处理中均衡多个位线的均衡电路，选择多个位线中的至少一个位线的多路复用电路位线的多个字线控制电路，控制多个字线中的一个字线的选择的多个字线控制电路;向多个字线控制电路提供第一电源电压的第一电压发生器，以及提供第二电压的第二电压发生器电源电压低于第一电源电压到均衡电路和多路复用电路。版权所有（C）2006，JPO＆NCIPI

23. 发明专利

JP2005267787A Two stage inside voltage generating circuit and method 有权
标题翻译：电压发生电路和方法两级
公开(公告)号：JP2005267787A
公开(公告)日：2005-09-29
申请号：JP2004080708
申请日：2004-03-19
申请人： Winbond Electron Corp , ウインボンドエレクトロニクスコーポレイションWinbond Electronics Corp.
发明人： CHEN CHIENG-CHUNG
IPC分类号： G11C11/407
摘要： PROBLEM TO BE SOLVED: To provide an inside voltage generating circuit whose power consumption is reduced and which is suitable for a low power consumption integrated circuit.
SOLUTION: This two stage inside voltage generating circuit includes a first inside voltage generating circuit generating first inside voltage in accordance with inputted external voltage; and a second inside voltage generating circuit generating second inside voltage, wherein the second inside voltage generating circuit has lower power consumption than the first inside voltage generating circuit. When external voltage is input, the first inside voltage generating circuit generates the first inside voltage, and the second inside voltage generating circuit generates the second inside voltage. After the second inside voltage is stabilized, the first inside voltage generating circuit stops the generation of the first inside voltage.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供功耗降低并适合于低功耗集成电路的内部电压产生电路。解决方案：该二级内部电压产生电路包括：第一内部电压产生电路，根据输入的外部电压产生第一内部电压; 以及产生第二内部电压的第二内部电压产生电路，其中所述第二内部电压产生电路具有比所述第一内部电压产生电路低的功率消耗。当输入外部电压时，第一内部电压产生电路产生第一内部电压，第二内部电压产生电路产生第二内部电压。在第二内部电压稳定之后，第一内部电压发生电路停止第一内部电压的产生。版权所有（C）2005，JPO＆NCIPI

24. 发明专利

JP2003317480A Two phase pre-charge circuit, and cancel circuit for current at standby of short circuit of dram 有权
标题翻译：两相短路电路中的电流和取消电路的短路电路
公开(公告)号：JP2003317480A
公开(公告)日：2003-11-07
申请号：JP2003088683
申请日：2003-03-27
申请人： Winbond Electron Corp , ウインボンドエレクトロニクスコーポレイション
发明人： CHEN CHIENG CHUNG
IPC分类号： G11C11/409 , G11C7/12 , G11C11/401 , G11C11/4094
CPC分类号： G11C7/12 , G11C11/4094 , G11C2207/2227
摘要： PROBLEM TO BE SOLVED: To provide a two phase pre-charge circuit coping with quality request for a low power DRAM element and a cancel circuit for current at the time of standby of short circuit of a DRAM element constituted by combining the circuits.
SOLUTION: A two phase pre-charge circuit is operated so that voltage by a pre-charge voltage source is applied to bit lines in an operation mode period, but the circuit is turned to be in an off-state in a standby mode period. Therefore, a current when standby caused by short circuit of a bit line and a word line is cancelled.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种双相预充电电路，其应对低功率DRAM元件的质量要求和在待组合DRAM组件的DRAM元件短路时的电流消除电路。
解决方案：操作两相预充电电路，使得在运行模式周期中，通过预充电电压源的电压施加到位线，但是电路在待机状态下变为截止状态模式周期。因此，取消了由位线和字线的短路引起的备用电流。版权所有（C）2004，JPO

25. 发明专利

JP2009300185A Circuit group, its test method, and test device 有权
标题翻译：电路集团，其测试方法和测试设备
公开(公告)号：JP2009300185A
公开(公告)日：2009-12-24
申请号：JP2008153407
申请日：2008-06-11
申请人： Winbond Electron Corp , ウインボンドエレクトロニクスコーポレイションWinbond Electronics Corp.
发明人： YANG CHENG KUANG
IPC分类号： G01R31/28
摘要： PROBLEM TO BE SOLVED: To provide a circuit group, its test method and a test device.
SOLUTION: The test method includes: a step of regulating a first voltage of a first circuit into a second voltage neared to a reference voltage rather than the first voltage based on a first regulation signal; a step of regulating a third voltage of a second circuit into a fourth voltage neared to the reference voltage rather than the third voltage based on a second regulation signal; and a step of regulating margin ranges of the second voltage and the fourth voltage together based on a margin regulation signal. Thereby, test times of the first circuit and the second circuit are shortened to save a cost.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供电路组，其测试方法和测试装置。解决方案：测试方法包括：基于第一调节信号将第一电路的第一电压调节成接近参考电压而不是第一电压的第二电压的步骤; 基于第二调节信号将第二电路的第三电压调节成接近参考电压而不是第三电压的第四电压的步骤; 以及基于余量调整信号一起调整第二电压和第四电压的余量范围的步骤。因此，缩短了第一电路和第二电路的测试时间以节省成本。版权所有（C）2010，JPO＆INPIT

26. 发明专利

JP2004180300A Ultrasonic identification apparatus and method 有权
公开(公告)号：JP2004180300A
公开(公告)日：2004-06-24
申请号：JP2003389046
申请日：2003-11-19
申请人： Winbond Electron Corp , ウインボンドエレクトロニクスコーポレイションWinbond Electronics Corp.
发明人： CHEN MAO-SONG , HO CHIN-TE
IPC分类号： H04B1/59 , G01S13/82 , G06K7/00 , H04B7/26
CPC分类号： G06K7/10039 , G01S13/82 , G06K7/0008
摘要： PROBLEM TO BE SOLVED: To provide an ultrasonic identification (RFID) apparatus equipped with a detector and several identification tags. SOLUTION: The detector transmits a time slot cycle signal and each cycle signal is divided into several slots. The identification tag receives the time slot cycle signal and each tag is provided with a random generator for generating a random number. Each identification tag responds to the detector in the related time slot corresponding to the random number generated by the random generator in each signal time slot cycle. COPYRIGHT: (C)2004,JPO

27. 发明专利

JP2004047934A Plug device having low contact resistance and method for manufacturing plug device 审中-公开
公开(公告)号：JP2004047934A
公开(公告)日：2004-02-12
申请号：JP2003005754
申请日：2003-01-14
申请人： Toshiba Corp , Winbond Electron Corp , ウインボンドエレクトロニクスコーポレイションWinbond Electronics Corp. , 株式会社東芝
发明人： CHEN NENG-KUO , NAKAJIMA KAZUAKI
IPC分类号： H01L21/28 , H01L21/285 , H01L21/768 , H01L23/485
CPC分类号： H01L21/76843 , H01L21/28512 , H01L21/28525 , H01L21/28568 , H01L21/76802 , H01L21/76831 , H01L21/76846 , H01L21/76849 , H01L21/76855 , H01L21/76864 , H01L21/76867 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a plug device having low contact resistance.
SOLUTION: In the method for manufacturing the plug device having low contact resistance, a silicon substrate and a BPSG layer covering the surface of the silicon substrate are formed. The silicon substrate has a dopant area. The BPSG layer is etched so as to form a contact window adjacent to the dopant area. When boron is doped in the dopant area, a silicon germanium layer is formed in the dopant area as a barrier layer. The barrier layer is formed adjacent to the contact window and a metallic plug surrounded by the barrier layer is formed. After forming a conductive connection line on the BPSG layer, rapid temperature annealing is performed to reactivate the dopant area. When boron is doped in the dopant area, the silicon germanium layer prevents the boron from shifting to the barrier layer to reduce the contact resistance of the plug device.
COPYRIGHT: (C)2004,JPO

28. 发明专利

JP2004023042A Semiconductor device and its manufacturing process 审中-公开
公开(公告)号：JP2004023042A
公开(公告)日：2004-01-22
申请号：JP2002179742
申请日：2002-06-20
申请人： Fujitsu Ltd , Toshiba Corp , Winbond Electron Corp , ウィンボンドエレクトロニクスコープWinbond ElectronicsCorp. , 富士通株式会社 , 株式会社東芝
发明人： KIYOTOSHI MASAHIRO , YAMAZAKI SOICHI , EGUCHI KAZUHIRO , NAKAHIRA JUNYA , SHU SOMEI
IPC分类号： C23C16/40 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having an easy-to-fabricate capacitor element in which electric characteristics can be enhanced. SOLUTION: After the surface of a semiconductor substrate 7 on which a transistor 3, and the like, are formed is coated with an interlayer insulation film 6, a lower electrode 11a for a capacitor is formed of ruthenium. A layer 15 of an Sr oxide forming the site A of perovskite structure is provided to cover the exposed surface of the lower electrode 11a. A first layer STO film 17a composed of a metal oxide having perovskite structure and becoming the underlying dielectric film 16a of the capacitor dielectric film 16 is formed to cover the exposed surface of the Sr oxide layer 15. A second layer STO film 17b becoming the overlying dielectric film 16b is formed to cover the exposed surface of the STO film 17a. An upper electrode 11b for capacitor is then formed of ruthenium on the exposed surface of the overlying dielectric film 16b, thus fabricating the capacitor element 10. COPYRIGHT: (C)2004,JPO

29. 发明专利

JP2003297950A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2003297950A
公开(公告)日：2003-10-17
申请号：JP2002094633
申请日：2002-03-29
申请人： Fujitsu Ltd , Toshiba Corp , Winbond Electron Corp , ウィンボンドエレクトロニクスコープ , 富士通株式会社 , 株式会社東芝
发明人： NAKANISHI TOSHIRO , OZAWA YOSHIO , CHAN SHUU-EN
IPC分类号： H01L21/76 , H01L21/8234 , H01L21/8242 , H01L27/08 , H01L27/088 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can avoid a lowering in reliability of a gate insulation film caused by height difference of an embedding oxide film by an STI method between a memory cell region and a peripheral circuit region and improve withstand voltage property of a gate insulation film, and to provide its manufacturing method.
SOLUTION: The semiconductor device has a silicon substrate 10 with a memory cell region and a peripheral circuit region, a silicon oxide film 16a which is embedded in a memory cell region 12 of the silicon substrate 10 and defines an element active region in the memory cell region 12 and a silicon oxide film 16a which is embedded in a peripheral circuit region 14 of the silicon substrate 10 and defines an element active region in the peripheral circuit region 14. The height of the surface of the silicon oxide film 16b is higher than that of the surface of the silicon oxide film 16a.
COPYRIGHT: (C)2004,JPO
摘要翻译：解决的问题：提供一种半导体器件，其可以避免由存储单元区域和外围电路区域之间的STI方法引起的嵌入氧化膜的高度差引起的栅极绝缘膜的可靠性降低，并且改善提供栅极绝缘膜的耐压性，并提供其制造方法。解决方案：半导体器件具有带有存储单元区域和外围电路区域的硅衬底10，硅衬底10嵌入在硅衬底10的存储单元区域12中并限定元件有源区域的氧化硅膜16a 存储单元区域12和硅衬底10的外围电路区域14中的氧化硅膜16a，并且在外围电路区域14中限定元件有源区。氧化硅膜16b的表面的高度为高于氧化硅膜16a的表面。版权所有（C）2004，JPO

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