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11. 发明专利

JP2000175213A METHOD FOR TRANSFERRING DIGITAL VIDEO/AUDIO DATA AND ITS SYSTEM 失效
公开(公告)号：JP2000175213A
公开(公告)日：2000-06-23
申请号：JP34625198
申请日：1998-12-04
申请人： NEC CORP
发明人： NOGUCHI TOSHIYUKI
IPC分类号： H04N5/00 , H04N9/65 , H04N9/66
摘要： PROBLEM TO BE SOLVED: To transfer digital video/audio data of many kinds of digital TV broadcast programs by adopting a signal processing based on the existing NTSC system and utilizing diversified transmission media. SOLUTION: A transmitter TX encodes input serial data on the basis of the NTSC system to generate an NTSC composite signal. The NTSC composite signal is modulated at a high frequency and the modulated signal is transmitted through a coaxial cable 15 placed between an RF modulation section 14 and an RF demodulation section 20 in a wired way or transferred by means of plural kinds of transmission media such as radio wave transmission and radio in response to transmission. A receiver RX receives the NTSC composite signal transferred through a transmission medium, decodes the signal on the basis of the NTSC system and transmits output serial data generated through decoding.

12. 发明专利

JP3046992B2 失效
公开(公告)号：JP3046992B2
公开(公告)日：2000-05-29
申请号：JP27237493
申请日：1993-10-29
IPC分类号： H04N9/64 , H04N9/65

13. 发明专利

JP2000102029A VIDEO SIGNAL PROCESSOR 失效
公开(公告)号：JP2000102029A
公开(公告)日：2000-04-07
申请号：JP26463798
申请日：1998-09-18
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： YAMAUCHI EIJI
IPC分类号： H04N9/65 , H04N9/68
摘要： PROBLEM TO BE SOLVED: To provide a video signal processor capable of constituting an encoder circuit for generating chrominance signals and a synchronizing signal generation circuit for generating synchronizing signals entirely by digital circuits even in the case that the deviation of a frame frequency to be synchronized is large and being extremely stable against power supply voltage fluctuation, temperature change and in the lapse of time. SOLUTION: A synchronizing signal generator 9 uses frame frequency information FRP extracted in a receiver 2 and a clock signal clk2 and counts the number of clocks within one frame indicated by the frame frequency information FRP. Then, from a counted result, the synchronizing signals for which a clock number N (N is an integer) is allocated to a valid line and the clock number M (M is the integer) is allocated to a blanking line inserted for at least one or more lines per frame are generated. Also, a chroma decoder 8 varies a color sub carrier wave frequency based on the information M and N of the clock number of one line.

14. 发明专利

JP3021140B2 失效
公开(公告)号：JP3021140B2
公开(公告)日：2000-03-15
申请号：JP30623691
申请日：1991-11-21
IPC分类号： H04N9/64 , H04N9/65 , H04N11/04

15. 发明专利

JPH11252579A DIGITAL ENCODER 失效
公开(公告)号：JPH11252579A
公开(公告)日：1999-09-17
申请号：JP4743698
申请日：1998-02-27
申请人： SONY CORP
发明人： YAMAUCHI ETSURO
IPC分类号： H04N7/01 , H04N9/65
摘要： PROBLEM TO BE SOLVED: To reduce the circuit scale of the entire device by conducting processing of 1st and 2nd color difference information by one system. SOLUTION: Input information from an input terminal 1 is fed to data latch circuits 2, 3 and luminance information (Y) and 1st and 2nd color difference information sets (Cb , Cr ) are separated. The separated color difference information sets are fed to an interpolation circuit 6, from which interpolated information is fed to a multiplexer circuit 8 via a low pass filter 7. Furthermore, sine and cosine waveform information sets from terminals 9, 10 are fed to a selector circuit 11, and the waveform information selected alternately is fed to a multiplier circuit 8 at a timing (unit delay time) when the 1st and 2nd color difference information sets are provided. The selected waveform information is multiplied with the 1st and 2nd color difference information sets to conduct orthogonal biaxial modulation. Then the modulated color difference information sets are fed to an adder circuit 12, in which the information is added to information delayed by a unit delay time and the result is extracted at an output terminal 14.

16. 发明专利

JPH11243555A METHOD AND CIRCUIT FOR CONVERTING CHROMINANCE SIGNAL IN NTSC 失效
公开(公告)号：JPH11243555A
公开(公告)日：1999-09-07
申请号：JP5900798
申请日：1998-02-24
申请人： FUJITSU GENERAL LTD
发明人： TAKAGI NOBUYUKI , ONODERA JUNICHI
IPC分类号： H04N9/65
摘要： PROBLEM TO BE SOLVED: To provide a method and circuit for converting a chrominance signal in NTSC, whcih makes a converter single a unit and can generate a C signal at the same time as the conversion. SOLUTION: For the conversion method of the chrominance signal in NTSC to be outputted by converting into each output chrominance signal C of B-Y, R-Y, -(B-Y) and -(R-Y), based on color difference input signals I, Q in an NTSC system, a coefficient selector 21 multiplies the inputted I, Q signals and inverted -I, -Q signals respectively to cos components and sin components as coefficients, to make respectively four kinds of cos components and sin components and a C signal generation part 23 combines respectively one different coefficients from among the four kinds of cos components and sin components and add them to generate a C signal. According to this chrominance signal converting method, only the conversion of C=Acos 33 deg.+Bsin 33 deg. is executed, and others can be obtained by merely controlling the combination of coefficients A and B.

17. 发明专利

JPH10336689A DIGITAL ENCODER 失效
公开(公告)号：JPH10336689A
公开(公告)日：1998-12-18
申请号：JP14028697
申请日：1997-05-29
申请人： SONY CORP
发明人： MIYAZAKI HARUOMI
IPC分类号： H04N9/65
摘要： PROBLEM TO BE SOLVED: To form carrier chrominance signals without the degradation of the S/N or the like by simple constitution. SOLUTION: Digital video signals from an input terminal 1 and a master clock from the input terminal 2 are supplied to a demultiplex and level translator circuit 3 and digital luminance signals (Y) and digital U signals (U) and V signals (V) are separated and taken out. The digital luminance signals (Y) are supplied through a delay circuit 4 to an arithmetic circuit 5. Also, the digital U signals (U) and V signals (V) are respectively supplied through low-pass filters 6 and 7 to a modulation circuit 8. Further, the master clock of a normal phase from the input terminal 2 and the master clock of an opposite phase through an inverter 9 are supplies to a read-only memory 10 storing the data of sine waves, the read data of the sine waves are supplied to the generation circuit 11 of sub carrier wave signals and prescribed sub carrier wave signals are generated and supplied to the modulation circuit 8.

18. 发明专利

JPH09322189A DIGITAL COLOR SIGNAL MODULATOR 失效
公开(公告)号：JPH09322189A
公开(公告)日：1997-12-12
申请号：JP15772696
申请日：1996-05-29
申请人： OKI MICRO DESIGN MIYAZAKI KK , OKI ELECTRIC IND CO LTD
发明人： TAKEI AKIHIRO
IPC分类号： H04N9/65
摘要： PROBLEM TO BE SOLVED: To obtain the color signal modulator in which a multiplier and a ROM to multiply sin and cos waves are not required and modulation is conducted with a simple circuit scale. SOLUTION: U and V components of each digital color signal from 1st and 3nd selectors 1, 2 are fed to a 3rd elector 3 for 1/2 cycle each, the 3rd selector 3 selects the signals alternately and a signal output synthesized by a frequency of a subcarrier is obtained. In the case of sine wave modulation or cos wave modulation, since an input signal is inverted periodically, a modulation output is obtained from a 4th selector 4 by alternately selecting an output of a through- path 6 and an inverted path 7.

19. 发明专利

JP2680765B2 失效
公开(公告)号：JP2680765B2
公开(公告)日：1997-11-19
申请号：JP34661691
申请日：1991-12-27
IPC分类号： H04N9/65 , H04N11/20

20. 发明专利

JPH09284789A SYNCHRONIZATION SYSTEM FOR IMAGE SIGNAL PROCESSING SYSTEM 失效
公开(公告)号：JPH09284789A
公开(公告)日：1997-10-31
申请号：JP9690896
申请日：1996-04-18
申请人： VICTOR COMPANY OF JAPAN
发明人： KITAMURA HIROYUKI , YOSHIDA SEIJI
IPC分类号： H04N5/232 , H04N9/09 , H04N9/65 , H04N11/06 , H04N11/24
摘要： PROBLEM TO BE SOLVED: To provide a synchronization system for an image signal processing system from which a High Vision system image signal is outputted by employing a solid-state image pickup element for a standard television system image signal with a simple configuration. SOLUTION: In this system, no PLL circuit is used and no phase comparator is used because an image pickup device and an image signal processing unit are synchronized only with transmission of a frame pulse, and a single crystal oscillator 31 is adopted for a voltage-controlled crystal oscillator. When a changeover switch 35 is used to select an output oscillation signal from an NTSC crystal oscillator 34, the image pickup device and the image signal processing unit are operated by the same frame frequency of nearly 29.97Hz. In the case that an output oscillation signal from a High Vision crystal oscillator 33 is selected, an error of nearly a half of a line of the NTSC system is produced for a frame period. Various timing signal generator 32 for the image pickup device is reset by the frame period of the image signal processing unit regardless of the error. A reset timing is taken within a vertical blanking period of the image pickup device.

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