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11. 发明专利

JP2009076681A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009076681A
公开(公告)日：2009-04-09
申请号：JP2007244323
申请日：2007-09-20
申请人： Toshiba Corp , 株式会社東芝
发明人： KONO HIROSHI , SHINOHE TAKASHI , OTA CHIHARU , NISHIO JOJI
IPC分类号： H01L29/12 , H01L21/336 , H01L29/739 , H01L29/78
CPC分类号： H01L29/66068 , H01L29/086 , H01L29/0878 , H01L29/0886 , H01L29/1095 , H01L29/1608 , H01L29/7395 , H01L29/7802
摘要： PROBLEM TO BE SOLVED: To reduce variation in channel length of an SiC MOSFET.
SOLUTION: A semiconductor device includes: a first silicon carbide layer (2) of a first conductivity type provided on a silicon carbide substrate; a second silicon carbide layer (3) of a second conductivity type formed on the first silicon carbide layer (2); first and second silicon carbide regions (4, 5) of a first conductivity type provided on a surface of the second silicon carbide layer (3), facing each other at a predetermined interval and having the same concentration and same depth; a third SiC region (9) extending through the first silicon carbide region (1) and second silicon carbide layer (3) and reaching the first silicon carbide layer; a gate insulator film (10
1 ) formed continuously on the first and second silicon carbide regions (4, 5) and the second silicon carbide layer (3) interposed therebetween; and a gate electrode (11) formed on the gate insulator film (10
1 ).
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：减少SiC MOSFET的沟道长度的变化。解决方案：半导体器件包括：设置在碳化硅衬底上的第一导电类型的第一碳化硅层（2）; 形成在第一碳化硅层（2）上的第二导电类型的第二碳化硅层（3）; 设置在第二碳化硅层（3）的表面上的第一和第二碳化硅区域（4,5），以预定间隔彼此面对并具有相同的浓度和相同的深度; 延伸穿过第一碳化硅区域（1）和第二碳化硅层（3）并到达第一碳化硅层的第三SiC区域（9）在第一和第二碳化硅区域（4,5）和第二碳化硅层（3）之间连续形成的栅绝缘膜（10 SB> 1）以及形成在栅极绝缘膜（10 SB> 1）上的栅电极（11）。版权所有（C）2009，JPO＆INPIT

12. 发明专利

JP2015056471A 半導体装置及びその製造方法有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2015056471A
公开(公告)日：2015-03-23
申请号：JP2013188156
申请日：2013-09-11
申请人：株式会社東芝 , Toshiba Corp
发明人： KONO HIROSHI , OHARA RYOICHI
IPC分类号： H01L29/861 , H01L21/28 , H01L21/329 , H01L29/41 , H01L29/868
CPC分类号： H01L29/872 , H01L21/18 , H01L29/0619 , H01L29/0688 , H01L29/0692 , H01L29/1608 , H01L29/66068 , H01L29/66212 , H01L29/66333 , H01L29/7395 , H01L29/7811 , H01L29/861 , H01L29/8611 , H01L2924/12032 , H01L2924/12036
摘要：【課題】サージ耐量の向上を図ることができる半導体装置を提供すること。【解決手段】実施形態に係る半導体装置は、第1半導体領域、第2半導体領域、第3半導体領域、第1電極及び第2電極を含む。第1半導体領域は第1導電形を有する。第1電極は、第1半導体領域とショットキー接合される。第2半導体領域は第2導電形を有し、第1半導体領域と第1電極との間に設けられる。第3半導体領域は第2導電形を有し、第1半導体領域と第1電極との間に設けられる。第3半導体領域は第1電極とオーミック接合される。第3半導体領域は、第1部分と、第1部分の深さよりも深い第2部分と、を有する。第3半導体領域の第1半導体領域側は、第1部分と第2部分とにより凹凸形状が構成される。第2電極は第1半導体領域の第1電極とは反対側に設けられる。【選択図】図1
摘要翻译：要解决的问题：提供可以实现耐浪涌电流改善的半导体器件。解决方案：根据实施例的半导体器件包括第一半导体区域，第二半导体区域，第三半导体区域，第一电极和第二半导体区域电极。第一半导体区域具有第一导电类型。第一电极与第一半导体区域形成肖特基结。第二半导体区域具有第二导电类型并且设置在第一半导体区域和第一电极之间。第三半导体区域具有第二导电类型并且设置在第一半导体区域和第一电极之间。第三半导体区域与第一电极形成欧姆结。第三半导体区域具有比第一部分的深度更深的第一部分和第二部分。第一半导体区域侧的第三半导体区域由第一部分和第二部分形成为凸凹形状。第二电极设置在与第一电极相对的一侧上的第一半导体区域上。

13. 发明专利

JP2013201400A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013201400A
公开(公告)日：2013-10-03
申请号：JP2012070391
申请日：2012-03-26
申请人： Toshiba Corp , 株式会社東芝
发明人： ARIYOSHI KEIKO , SUZUKI TAKUMA , KONO HIROSHI , SHINOHE TAKASHI
IPC分类号： H01L29/78 , H01L21/336 , H01L29/06 , H01L29/12
CPC分类号： H01L29/7889 , H01L29/045 , H01L29/1608 , H01L29/407 , H01L29/42368 , H01L29/66068 , H01L29/66825 , H01L29/7813
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device using SiC with improved withstand voltage, and to provide a method of manufacturing the same.SOLUTION: A semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a control electrode, a floating electrode, and an insulating film. The first semiconductor region contains silicon carbide. The second semiconductor region is provided on the first semiconductor region and contains silicon carbide of a first conductivity type. The third semiconductor region is provided on the second semiconductor region and contains silicon carbide of the second conductivity type. The fourth semiconductor region is provided on the third semiconductor region and contains silicon carbide of the first conductivity type. The control electrode is provided in a trench provided in the fourth semiconductor region, the third semiconductor region, and the second semiconductor region. The floating electrode is provided between the control electrode and a bottom surface of the trench. The insulating film is provided between the trench and the control electrode, between the trench and the floating electrode, and between the control electrode and the floating electrode.
摘要翻译：要解决的问题：提供一种使用具有改善的耐电压的SiC的半导体器件，并提供其制造方法。解决方案：半导体器件包括第一半导体区域，第二半导体区域，第三半导体区域，第四半导体区域，控制电极，浮动电极和绝缘膜。第一半导体区域包含碳化硅。第二半导体区域设置在第一半导体区域上并且包含第一导电类型的碳化硅。第三半导体区域设置在第二半导体区域上并且包含第二导电类型的碳化硅。第四半导体区域设置在第三半导体区域上并且包含第一导电类型的碳化硅。控制电极设置在设置在第四半导体区域，第三半导体区域和第二半导体区域中的沟槽中。浮置电极设置在控制电极和沟槽的底表面之间。绝缘膜设置在沟槽和控制电极之间，沟槽和浮动电极之间以及控制电极和浮动电极之间。

14. 发明专利

JP2013182905A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013182905A
公开(公告)日：2013-09-12
申请号：JP2012043648
申请日：2012-02-29
申请人： Toshiba Corp , 株式会社東芝
发明人： KONO HIROSHI , SHINOHE TAKASHI , SUZUKI TAKUMA , NISHIO JOJI
IPC分类号： H01L29/78 , H01L29/12 , H01L29/739
CPC分类号： H01L29/1608 , H01L29/0696 , H01L29/086 , H01L29/1045 , H01L29/1095 , H01L29/7395 , H01L29/7802
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that attains low ON resistance and a stable withstand voltage, and has improved unbalance tolerance.SOLUTION: A semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, an insulation film, a control electrode, and a first electrode and a second electrode. The first semiconductor region includes silicon carbide of a first conductivity type and has a first portion. The second semiconductor region is on the upper side of the first semiconductor region and provided adjacent to the first portion, and includes silicon carbide of a second conductivity type. The third semiconductor region is on the upper side of the second semiconductor region and provided apart from the first portion, and includes silicon carbide of a first conductivity type. The fourth semiconductor region is provided on the upper side of the second semiconductor region, and includes silicon carbide of a second conductivity type. Regions of the second semiconductor region on the sides contacting the third semiconductor region and the fourth semiconductor region have a higher impurity concentration than on the side contacting the first portion.
摘要翻译：要解决的问题：提供一种获得低导通电阻和稳定的耐受电压并且具有改善的不平衡公差的半导体器件。解决方案：半导体器件包括第一半导体区域，第二半导体区域，第三半导体区域，第四半导体区域半导体区域，绝缘膜，控制电极以及第一电极和第二电极。第一半导体区域包括第一导电类型的碳化硅并具有第一部分。第二半导体区域位于第一半导体区域的上侧，并且与第一部分相邻地设置，并且包括第二导电类型的碳化硅。第三半导体区域位于第二半导体区域的上侧，并且与第一部分分开设置，并且包括第一导电类型的碳化硅。第四半导体区域设置在第二半导体区域的上侧，并且包括第二导电类型的碳化硅。与第三半导体区域和第四半导体区域接触的侧面上的第二半导体区域的区域的杂质浓度高于与第一部分接触的一侧的杂质浓度。

15. 发明专利

JP2013084990A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2013084990A
公开(公告)日：2013-05-09
申请号：JP2013003530
申请日：2013-01-11
申请人： Toshiba Corp , 株式会社東芝
发明人： KONO HIROSHI , SHINOHE TAKASHI , MIZUKAMI MAKOTO
IPC分类号： H01L29/12 , H01L21/336 , H01L29/739 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device that uses SiC, allows microfabrication, and has ultra low on-resistance and excellent reliability.SOLUTION: A method of manufacturing a semiconductor device comprises the steps of: forming a first silicon carbide layer 14 of a first conductivity type on a first primary surface of a silicon carbide substrate 12; forming a first silicon carbide region 16 by ion-injecting a second-conductivity-type impurity into the first silicon carbide layer; forming a second silicon carbide region 18 by ion-injecting a first-conductivity-type impurity into the first silicon carbide layer; forming a third silicon carbide region 20 by ion-injecting the second-conductivity-type impurity into the first silicon carbide layer; forming a gate insulating film; forming a gate electrode; forming an interlayer insulating film; forming a trench that penetrates through the second silicon carbide region and reaches the third silicon carbide region; forming a first electrode 24 containing a metal element on the second silicon carbide region on a side surface of the trench; forming a second electrode 26 containing Al on the third silicon carbide region on the bottom surface of the trench; forming a first main electrode 34 on the second electrode; and forming a second main electrode on a second primary surface of the silicon carbide substrate.
摘要翻译：要解决的问题：提供一种制造使用SiC的半导体器件的方法，允许微细加工，并且具有超低的导通电阻和优异的可靠性。解决方案：制造半导体器件的方法包括以下步骤：在碳化硅衬底12的第一主表面上形成第一导电类型的第一碳化硅层14; 通过将第二导电型杂质离子注入第一碳化硅层来形成第一碳化硅区域16; 通过将第一导电型杂质离子注入第一碳化硅层来形成第二碳化硅区域18; 通过将第二导电型杂质离子注入到第一碳化硅层中形成第三碳化硅区域20; 形成栅极绝缘膜; 形成栅电极; 形成层间绝缘膜; 形成穿过所述第二碳化硅区域并到达所述第三碳化硅区域的沟槽; 在沟槽的侧表面上形成在第二碳化硅区域上含有金属元素的第一电极24; 在沟槽的底表面上形成在第三碳化硅区域上含有Al的第二电极26; 在第二电极上形成第一主电极34; 以及在所述碳化硅衬底的第二主表面上形成第二主电极。版权所有（C）2013，JPO＆INPIT

16. 发明专利

JP2009182271A Silicon carbide semiconductor device 审中-公开
标题翻译：硅碳化硅半导体器件
公开(公告)号：JP2009182271A
公开(公告)日：2009-08-13
申请号：JP2008022001
申请日：2008-01-31
申请人： Toshiba Corp , 株式会社東芝
发明人： SUZUKI TAKUMA , KONO HIROSHI , SHINOHE TAKASHI
IPC分类号： H01L29/12 , H01L29/739 , H01L29/78
CPC分类号： H01L29/41766 , H01L21/0465 , H01L29/086 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/42368 , H01L29/45 , H01L29/66068 , H01L29/7395 , H01L29/7802 , H01L29/7816
摘要： PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device of which the reliability of a gate insulating film is improved. SOLUTION: The silicon carbide semiconductor device includes a silicon carbide substrate (101) having a first main plane and a second main plane, a silicon carbide layer (102) of first conductive type provided in the first main plane of the silicon carbide substrate, a first silicon carbide region (103) of second conductive type provided in the surface of the silicon carbide layer, a second silicon carbide region (104) of first conductive type provided in the surface of the first silicon carbide region, a gate insulating film (105) which is provided selectively astride the portion where the silicon carbide layer, the first silicon carbide region, and the second silicon carbide region range continuously, a gate electrode (106) formed on the gate insulating film, a first electrode (108) embedded in a trench selectively provided in a portion adjacent to the second and the first silicon carbide region, and a second electrode (107) formed in the second main plane of the silicon carbide substrate. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种提高栅极绝缘膜的可靠性的碳化硅半导体器件。解决方案：碳化硅半导体器件包括具有第一主平面和第二主平面的碳化硅衬底（101），设置在碳化硅的第一主平面中的第一导电类型的碳化硅层（102）衬底，设置在碳化硅层的表面中的第二导电类型的第一碳化硅区域（103），设置在第一碳化硅区域的表面中的第一导电类型的第二碳化硅区域（104），栅绝缘层薄膜（105）选择性地横跨碳化硅层，第一碳化硅区域和第二碳化硅区域连续变化的部分，形成在栅极绝缘膜上的栅电极（106），第一电极（108）），其选择性地设置在与所述第二碳化硅区域和所述第一碳化硅区域相邻的部分中的沟槽中;以及第二电极（107），形成在所述碳化硅壳体的所述第二主平面中。。版权所有（C）2009，JPO＆INPIT

17. 发明专利

JP2008251772A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2008251772A
公开(公告)日：2008-10-16
申请号：JP2007090297
申请日：2007-03-30
申请人： Toshiba Corp , 株式会社東芝
发明人： OTA CHIHARU , NISHIO JOJI , SHINOHE TAKASHI , KONO HIROSHI
IPC分类号： H01L29/47 , H01L29/872
CPC分类号： H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a termination structure of a Schottky electrode by which a stable breakdown voltage is realized. SOLUTION: The semiconductor device has a semiconductor substrate 1 of a first conductivity type, a semiconductor layer 2 of a first conductivity type which is formed on the semiconductor substrate 1 and has an active region and an element termination region surrounding it, a first electrode 7 which is formed on the surface of the active region of the semiconductor layer 2 and forms a Schottky barrier against the semiconductor layer 2, a second electrode 10 which is formed on the backside of the semiconductor substrate 1, a first semiconductor region 3 of a second conductivity type which is formed from the end of the active region toward the element termination region, a second semiconductor region 4 of a second conductivity type which is formed under the end of the first electrode 7 on the inner surface of the first semiconductor region on the surface of the semiconductor layer 2 and a third electrode 11 which is electrically connected with the first electrode 7 on the second semiconductor region 4 and formed separately from the active region, and formed of a material different from that of the first electrode 7. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供实现稳定击穿电压的肖特基电极的端接结构。解决方案：半导体器件具有第一导电类型的半导体衬底1，第一导电类型的半导体层2，其形成在半导体衬底1上并且具有有源区和围绕其的元件终止区，第一电极7，其形成在半导体层2的有源区的表面上，并形成对半导体层2的肖特基势垒;形成在半导体衬底1的背面的第二电极10，第一半导体区域3 第二导电类型的第二半导体区域4，其形成在第一导电类型的第二导电类型的第二半导体区域4上，第二导电类型形成在第一半导体的内表面上的第一电极7的端部下方半导体层2的表面上的区域和在第二半导体上与第一电极7电连接的第三电极11 电导体区域4并且与有源区分开形成，并且由不同于第一电极7的材料形成。版权所有（C）2009，JPO＆INPIT

18. 发明专利

JP2006211429A Communication terminal device and control method thereof 有权
标题翻译：通信终端设备及其控制方法
公开(公告)号：JP2006211429A
公开(公告)日：2006-08-10
申请号：JP2005022236
申请日：2005-01-28
申请人： Toshiba Corp , 株式会社東芝
发明人： OHAMA JUNICHI , KONO HIROSHI
IPC分类号： H04M11/00 , G06F13/00 , H04M1/56 , H04M1/66
CPC分类号： H04L51/28 , H04L29/12009 , H04L29/12594 , H04L51/066 , H04L51/12 , H04L61/301 , H04L61/303 , H04L67/04
摘要： PROBLEM TO BE SOLVED: To provide a communication terminal device in which a mail limiting function can be effectively operated without increasing a mail address registered for the mail limiting function and to provide a control method thereof.
SOLUTION: A correspondence relation between a transformation source domain by an automatic address transformation function and a transformed domain is stored in a domain transformation table and by referring to the domain transformation table, the transformation source domain corresponding to the transformed domain is acquired from a domain of a mail address transformed by the automatic address transformation function. A mail address in which a domain of a mail address of transmitting/receiving mail is replaced with the acquired transformation source domain is compared with a registered mail address to limit the transmission/reception of the mail.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种通信终端设备，其中可以有效地操作邮件限制功能，而不增加为邮件限制功能注册的邮件地址，并提供其控制方法。解决方案：通过自动地址变换功能的变换源域与变换域之间的对应关系存储在域变换表中，并且通过参考域变换表，获取与变换域相对应的变换源域来自通过自动地址转换功能变换的邮件地址的域。将发送/接收邮件的邮件地址的域替换为所获取的转换源域的邮件地址与注册邮件地址进行比较，以限制邮件的发送/接收。版权所有（C）2006，JPO＆NCIPI

19. 发明专利

JP2006211428A Communication terminal device and its control method 有权
标题翻译：通信终端设备及其控制方法
公开(公告)号：JP2006211428A
公开(公告)日：2006-08-10
申请号：JP2005022235
申请日：2005-01-28
申请人： Toshiba Corp , 株式会社東芝
发明人： KONO HIROSHI , ITO YOSUKE
IPC分类号： H04M1/66 , H04W88/02
摘要： PROBLEM TO BE SOLVED: To provide a communication terminal device capable of ensuring the security of a security mail without increasing a memory region used for a regium function and a control method for the communication terminal device.
SOLUTION: When the security mail during an editing in a security mode and the editing operation of a normal mail are interrupted, the security mail and the normal mail are stored in the common conservation region of a regium DB 50. When the security mode is released when the security mail during the editing in the security mode is stored in the regium DB 50, the security mail is conserved forcibly to a security-mail transmitting-receiving box for a mail DB 70.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够确保安全邮件的安全性而不增加用于区域功能的存储区域和通信终端设备的控制方法的通信终端设备。
解决方案：当安全模式下的安全邮件和正常邮件的编辑操作中断安全邮件时，安全邮件和正常邮件都存储在regium DB 50的公共保护区域中。当安全邮件当在安全模式下的编辑期间的安全邮件被存储在登记DB 50中时，该安全邮件被强制地保存到用于邮件DB70的安全邮件发送接收箱。版权所有（C））2006年，日本特许厅和NCIPI

20. 发明专利

JP2011060939A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2011060939A
公开(公告)日：2011-03-24
申请号：JP2009207940
申请日：2009-09-09
申请人： Toshiba Corp , 株式会社東芝
发明人： NISHIO JOJI , OTA CHIHARU , SUZUKI TAKUMA , KONO HIROSHI , MIZUKAMI MAKOTO , SHINOHE TAKASHI
IPC分类号： H01L29/47 , H01L21/28 , H01L21/3205 , H01L21/336 , H01L23/52 , H01L29/12 , H01L29/78 , H01L29/872
CPC分类号： H01L29/7802 , H01L21/02378 , H01L21/02433 , H01L21/02529 , H01L21/02658 , H01L21/0495 , H01L21/30604 , H01L29/0878 , H01L29/1608 , H01L29/66068 , H01L29/66143 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of stably realizing a high yield of a large-scale semiconductor device even when a silicon carbide semiconductor including a defect is used. SOLUTION: The method of manufacturing the semiconductor device has a step of epitaxially growing a silicon carbide semiconductor layer on a silicon carbide semiconductor substrate, a step of polishing a surface of the silicon carbide semiconductor layer, a step of ion-implanting impurities into the silicon carbide semiconductor layer after the step of polishing, a step of performing heat treatment to activate the impurities, a step of forming a first thermal oxide film on the surface of the silicon carbide semiconductor layer after the step of performing heat treatment, a step of chemically removing the first thermal oxide film, and a step of forming an electrode layer on the silicon carbide semiconductor film. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：即使当使用包括缺陷的碳化硅半导体时，提供一种能够稳定地实现大规模半导体器件的高产率的半导体器件的制造方法。解决方案：制造半导体器件的方法具有在碳化硅半导体衬底上外延生长碳化硅半导体层的步骤，对碳化硅半导体层的表面进行抛光的步骤，离子注入杂质的步骤在抛光步骤之后进入碳化硅半导体层，进行热处理以激活杂质的步骤，在进行热处理的步骤之后在碳化硅半导体层的表面上形成第一热氧化膜的步骤，化学去除第一热氧化膜的步骤，以及在碳化硅半导体膜上形成电极层的步骤。版权所有（C）2011，JPO＆INPIT

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