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11. 发明专利

JP2008276002A Method for controlling photomask, method for generating number of times of cleansing photomask, and photomask control system 有权
标题翻译：控制光子的方法，产生清洗光时间的方法和光电子控制系统
公开(公告)号：JP2008276002A
公开(公告)日：2008-11-13
申请号：JP2007121027
申请日：2007-05-01
申请人： Toshiba Corp , 株式会社東芝
发明人： MUKAI HIDEFUMI , YAMAGUCHI SHINJI , ARISAWA YUKIYASU , KOTANI TOSHIYA
IPC分类号： G03F1/32 , G03F1/82 , G03F1/84 , H01L21/027
CPC分类号： G03F1/82 , G03F1/86
摘要： PROBLEM TO BE SOLVED: To provide a method for controlling a photomask for improving the yield of a semiconductor device and reducing the cost. SOLUTION: The method for controlling a photomask includes: a step (S1002) of cleaning a photomask; a step (S1003) of measuring at least one physical quantity in magnetic permeability and retardation of the photomask, the pattern dimension, the pattern height and the sidewall profile of the pattern after the cleaning step; steps (S1004, S1005) of measuring a two-dimensional feature of a preliminarily determined critical pattern in the photomask, after the cleaning step; a step (S1006) of obtaining a lithography margin, by executing lithography simulation on the measured two-dimensional feature by using the measured physical quantity; and a step (S1007) of deciding whether the photomask can be used, based on the obtained lithography margin. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于控制光掩模以提高半导体器件的产量并降低成本的方法。解决方案：用于控制光掩模的方法包括：清洁光掩模的步骤（S1002）; 测量清洁步骤之后的图案的磁导率和光掩模的延迟，图案尺寸，图案高度和侧壁轮廓中的至少一个物理量的步骤（S1003）在清洁步骤之后测量光掩模中预先确定的临界图案的二维特征的步骤（S1004，S1005）; 通过使用测量的物理量对所测量的二维特征进行光刻模拟，获得光刻裕度的步骤（S1006）; 以及基于获得的光刻裕度来决定是否可以使用光掩模的步骤（S1007）。版权所有（C）2009，JPO＆INPIT

12. 发明专利

JP2008233383A Pattern forming method, pattern forming program, manufacturing method of mask, and manufacturing method of semiconductor device 审中-公开
标题翻译：图案形成方法，图案形成程序，掩模制造方法和半导体器件的制造方法
公开(公告)号：JP2008233383A
公开(公告)日：2008-10-02
申请号：JP2007071031
申请日：2007-03-19
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO KENJI , TANAKA SATOSHI , KOTANI TOSHIYA , FUJISAWA TADAHITO , HASHIMOTO KOJI
IPC分类号： G03F1/68
CPC分类号： G03F1/00
摘要： PROBLEM TO BE SOLVED: To provide a pattern forming method with which a fine pattern formed by applying a side wall leaving process is efficiently and easily formed. SOLUTION: An endmost pattern 3a among a plurality of integrated circuit patterns 3 is selected. A first closest pattern 3b which is closest to the endmost pattern 3a is extracted from the respective integrated circuit patterns 3. A pattern 4 is generated which is circumscribed with the endmost pattern 3a and first closest pattern 3b. A non-overlap pattern 5 excluding portions overlapping with the endmost pattern 3a and first closest pattern 3b is generated from the circumscribed pattern 4. A second closest pattern 6 which is closest to the non-overlap pattern 5 is extracted from the respective integrated circuit patterns 3. Steps from the one of extracting the first closest pattern 3b from a second layer to the one of extracting the second closest pattern 6 are repeated until all the data of the respective integrated circuit patterns 3 are completely followed. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种图案形成方法，通过该图案形成方法能够有效且容易地形成通过施加侧壁离开处理而形成的精细图案。
解决方案：选择多个集成电路图案3中的最终图案3a。从各集成电路图案3提取最靠近最终图案3a的第一最近图案3b。产生与最末端图案3a和第一最近图案3b相切的图案4。从外接图案4生成除了与最终图案3a和第一最近图案3b重叠的部分的不重叠图案5.从各个集成电路图案中提取最接近非重叠图案5的第二最近图案6 重复将从第二层提取第一最近图案3b到提取第二最近图案6的步骤之间的步骤，直到完全遵循各个集成电路图案3的所有数据。版权所有（C）2009，JPO＆INPIT

13. 发明专利

JP2008058812A Method and program of creating mask drawing data of semiconductor device 审中-公开
标题翻译：创建半导体器件掩模数据的方法和程序
公开(公告)号：JP2008058812A
公开(公告)日：2008-03-13
申请号：JP2006237954
申请日：2006-09-01
申请人： Toshiba Corp , 株式会社東芝
发明人： NAKAJIMA FUMIHARU , KOTANI TOSHIYA
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , H01J37/305 , H01L21/027
摘要： PROBLEM TO BE SOLVED: To provide a method for creating mask drawing data of a semiconductor device with which a lithographic margin can be increased, while taking into consideration the mask dimension dispersion due to the mask process.
SOLUTION: The method includes steps of generating a first mask pattern by processing mask data from a design pattern (S101); classifying partial mask patterns, constituting the pattern based on shapes (S102); generating a second mask pattern by resizing each partial mask pattern based on the shapes (S103); calculating the planar shape of a resist pattern to be formed on a substrate, according to lithographic conditions (S104, S105); calculating the difference between the planar shape and the design pattern (S106); determining whether the difference satisfies preliminarily given conditions (S107); when the conditions are not satisfied, correcting a portion that produces the difference that does not satisfy the conditions of the design pattern (S109) and then returning to the step (S101) of generating the first mask pattern; and when the conditions are satisfied, the current first mask pattern is set as the mask drawing data (S108).
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于创建可以增加光刻裕度的半导体器件的掩模绘图数据的方法，同时考虑由于掩模处理引起的掩模尺寸色散。解决方案：该方法包括以下步骤：通过从设计模式处理掩模数据来产生第一掩模图案（S101）; 对部分掩模图案进行分类，根据形状构成图案（S102）; 通过基于所述形状来调整每个部分掩模图案的大小来生成第二掩模图案（S103）; 根据光刻条件计算要在基板上形成的抗蚀剂图案的平面形状（S104，S105）; 计算平面形状和设计图案之间的差异（S106）; 确定差异是否满足初步给定条件（S107）; 当不满足条件时，校正产生不符合设计图案的条件的差的部分（S109），然后返回到产生第一掩模图案的步骤（S101）; 并且当满足条件时，将当前第一掩模图案设置为掩模绘图数据（S108）。版权所有（C）2008，JPO＆INPIT

14. 发明专利

JP2008020734A Design pattern preparation method for semiconductor device, program, and method of manufacturing the semiconductor device 审中-公开
标题翻译：用于半导体器件的设计图案制备方法，程序和制造半导体器件的方法
公开(公告)号：JP2008020734A
公开(公告)日：2008-01-31
申请号：JP2006193130
申请日：2006-07-13
申请人： Toshiba Corp , 株式会社東芝
发明人： KOTANI TOSHIYA
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70
摘要： PROBLEM TO BE SOLVED: To provide a design pattern preparation method for a semiconductor device with high versatility, having sufficient process margin in lithographic process, a program making a computer execute the design pattern preparation method, and to provide a method of manufacturing the semiconductor device that forms a resist pattern on the semiconductor substrate, using the design pattern preparation method. SOLUTION: The design pattern preparation method for the semiconductor device includes a step (101) of generating a mask pattern from the design pattern of the semiconductor device, steps (102, 103) of calculating the planar shape of a resist pattern to be formed on the semiconductor substrate for each process condition, in accordance with two or more different process conditions from the mask pattern, a step (104) of calculating the difference between the planar shapes of the resist pattern, calculated for the respective process conditions, a step (105) of determining whether the difference satisfies a predefined condition, and a step (107) of correcting the design pattern that corresponds to the position, where the difference is occurring, when it is determined that the condition is not satisfied. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供具有高通用性的半导体器件的设计图案制备方法，在光刻工艺中具有足够的工艺裕度，使计算机执行设计图案制备方法的程序，并提供制造方法使用设计图案制备方法在半导体衬底上形成抗蚀剂图案的半导体器件。解决方案：半导体器件的设计图案制备方法包括从半导体器件的设计图案生成掩模图案的步骤（101），计算抗蚀剂图案的平面形状的步骤（102,103），以根据与掩模图案的两个或更多个不同的工艺条件，在每个处理条件的半导体衬底上形成用于计算针对各工艺条件计算的抗蚀剂图案的平面形状之间的差的步骤（104）确定差异是否满足预定条件的步骤（105）;以及当确定不满足条件时，校正与发生差异的位置相对应的设计模式的步骤（107）。版权所有（C）2008，JPO＆INPIT

15. 发明专利

JP2007142275A Phototmask determining method, semiconductor device manufacturing method, and its program 审中-公开
标题翻译：光电测定方法，半导体器件制造方法及其程序
公开(公告)号：JP2007142275A
公开(公告)日：2007-06-07
申请号：JP2005336183
申请日：2005-11-21
申请人： Toshiba Corp , 株式会社東芝
发明人： KOTANI TOSHIYA , FUKUHARA KAZUYA , DEWA KYOKO
IPC分类号： H01L21/027 , G03F7/20
CPC分类号： G03F7/70441
摘要： PROBLEM TO BE SOLVED: To provide a method for rapidly and adequately performing correspondence when an exposure device is changed. SOLUTION: The method comprises a process S1 for regulating the mask pattern of a photomask for a first exposure device; a process S2 for regulating a plurality of exposure conditions to be set in a second exposure device; a process S3 for predicting the projection image of the mask pattern to be projected on a substrate by the second exposure device concerning the respective exposure conditions; a process S4 for predicting the work pattern of a substrate surface, based on the projection image, concerning the respective exposure conditions; a process S7 for determining whether or not the work pattern satisfies a prescribed condition concerning the respective exposure conditions; and a process S11 for determining that the photomask is applied to the second exposure device, when the work pattern satisfies the prescribed condition concerning at least one exposure condition. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种当曝光装置改变时快速和充分地执行对应的方法。解决方案：该方法包括用于调节用于第一曝光装置的光掩模的掩模图案的工艺S1; 用于调节要设置在第二曝光装置中的多个曝光条件的处理S2; 用于通过第二曝光装置预测要在投影到基板上的掩模图案的投影图像关于各个曝光条件的处理S3; 用于基于投影图像预测基板表面的工作图案关于各个曝光条件的处理S4; 用于确定工作图案是否满足关于各个曝光条件的规定条件的处理S7; 以及当工件图案满足关于至少一个曝光条件的规定条件时，确定将光掩模应用于第二曝光装置的处理S11。版权所有（C）2007，JPO＆INPIT

16. 发明专利

JP2006053248A Method for creating design pattern data, method for creating mask pattern data, method for manufacturing mask, and method and program for manufacturing semiconductor device 审中-公开
标题翻译：用于创建设计图案数据的方法，用于创建掩模图形数据的方法，用于制造掩模的方法以及用于制造半导体器件的方法和程序
公开(公告)号：JP2006053248A
公开(公告)日：2006-02-23
申请号：JP2004233615
申请日：2004-08-10
申请人： Toshiba Corp , 株式会社東芝
发明人： KOTANI TOSHIYA , TANAKA SATOSHI , NOJIMA SHIGEKI , INOUE SOICHI
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , G06F17/50 , H01L21/027
CPC分类号： H01J37/3026 , G03F1/36 , G03F1/68
摘要： PROBLEM TO BE SOLVED: To provide a method for creating design pattern data to reduce the TAT (turn around time).
SOLUTION: The method for creating design pattern data includes: a step S1 of creating first mask pattern data based on first design pattern data; a step S5 of predicting a first wafer pattern to be formed on a wafer corresponding to the first mask pattern data based on the first mask pattern data; a step S6 of judging whether the difference between the first wafer pattern and first design pattern corresponding to the first design pattern data is within a preliminarily determined permissible variation amount or not; a step S7 of correcting the first design pattern data in a part corresponding to the difference if the difference is out of the permissible variation amount; and a step S10 of synthesizing the data obtained by eliminating the first design pattern data of the part corresponding to the corrected difference from the first design pattern data, with the first design pattern data in the part corresponding to the corrected difference, to create second design pattern data.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于创建设计模式数据以减少TAT（转向时间）的方法。解决方案：用于创建设计图案数据的方法包括：基于第一设计图案数据创建第一掩模图案数据的步骤S1; 步骤S5，基于第一掩模图案数据预测与第一掩模图案数据相对应的在晶片上形成的第一晶片图案; 判断与第一设计图案数据对应的第一晶片图案和第一设计图案之间的差是否在预先确定的允许变化量内的步骤S6; 如果差超出允许变化量，则校正与差异对应的部分中的第一设计模式数据的步骤S7; 以及步骤S10，通过从与第一设计图案数据相对应的与校正的差异相对应的部分的第一设计图案数据与通过对应于校正的差异的部分中的第一设计图案数据合成获得的数据，以创建第二设计模式数据。版权所有（C）2006，JPO＆NCIPI

17. 发明专利

JP2005208233A Exposure mask and method for forming pattern 审中-公开
标题翻译：曝光掩模和形成图案的方法
公开(公告)号：JP2005208233A
公开(公告)日：2005-08-04
申请号：JP2004013254
申请日：2004-01-21
申请人： Toshiba Corp , 株式会社東芝
发明人： HAYAZAKI KEI , CHIBA KENJI , KOTANI TOSHIYA , SHIBATA TAKESHI
IPC分类号： G03F1/68 , G03F1/70 , H01L21/027 , G03F1/08
摘要： PROBLEM TO BE SOLVED: To suppress dimensional changes in a pattern depending on a covering rate of the pattern, and to obtain a uniform pattern dimension.
SOLUTION: The exposure mask has first and second mask patterns comprising a coated region 32 by a light-shielding film and an opening region 33, disposed in the proximity to each other, and is used to expose a resist applied on a wafer to form in the resist a first resist pattern and a second resist pattern corresponding to the first mask pattern (cell region) and to the second mask pattern (dummy region), respectively. The quantity of transmitting light through the opening region 33 of the second mask pattern is controlled in such a manner that the average exposure light quantity, the average latent image strength or the average dissolving rate of the second resist pattern is almost equal to those of the first resist pattern.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：根据图案的覆盖率抑制图案中的尺寸变化，并获得均匀的图案尺寸。解决方案：曝光掩模具有第一和第二掩模图案，其包括由遮光膜和开口区域33彼此靠近设置的涂覆区域32，并且用于暴露施加在晶片上的抗蚀剂在抗蚀剂中分别形成对应于第一掩模图案（单元区域）和第二掩模图案（虚拟区域）的第一抗蚀剂图案和第二抗蚀剂图案。通过第二掩模图案的开口区域33的透射光的量被控制为使得第二抗蚀剂图案的平均曝光量，平均潜像强度或平均溶解速率几乎等于第一抗蚀剂图案。版权所有（C）2005，JPO＆NCIPI

18. 发明专利

JP2005181612A Pattern forming method, method for manufacturing mask, and method and program for manufacturing semiconductor device 有权
标题翻译：图案形成方法，制造掩模的方法以及制造半导体器件的方法和程序
公开(公告)号：JP2005181612A
公开(公告)日：2005-07-07
申请号：JP2003420984
申请日：2003-12-18
申请人： Toshiba Corp , 株式会社東芝
发明人： KIYOU SUIGEN , KOTANI TOSHIYA , INOUE SOICHI
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , G03F7/20 , G06F17/50 , H01L21/027 , G03F1/08
CPC分类号： G03F1/36 , G03F7/70441
摘要： PROBLEM TO BE SOLVED: To provide a pattern forming method in which a desired pattern can easily be formed.
SOLUTION: The pattern forming method for a semiconductor device includes a stage S5 of extracting a partial area from a pattern layout, a stage S6 of generating a perturbation pattern by imparting a perturbation to a pattern included in the partial area, a stage S7 of making specified corrections for the perturbation pattern, stages S8 and S9 of predicting a 1st pattern to be formed on a wafer from the perturbation pattern having been corrected as specified, a stage S10 of finding a 1st difference between the perturbation pattern and 1st pattern, and a stage S11 of storing information regarding the perturbation pattern including information regarding the 1st difference.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供可以容易地形成所需图案的图案形成方法。解决方案：半导体器件的图案形成方法包括从图案布局提取部分区域的阶段S5，通过对包括在部分区域中的图案赋予扰动来生成扰动图案的阶段S6，阶段 S7对于扰动图案进行指定的校正，通过从已经被指定的校正的扰动图案预测要在晶片上形成的第一图案的阶段S8和S9，找到扰动图案和第一图案之间的第一个差异的阶段S10 以及阶段S11，其存储关于包含关于第一差的信息的扰动模式的信息。版权所有（C）2005，JPO＆NCIPI

19. 发明专利

JP2003195473A METHOD FOR CORRECTING PATTERN AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003195473A
公开(公告)日：2003-07-09
申请号：JP2001398438
申请日：2001-12-27
申请人： TOSHIBA CORP
发明人： KOBAYASHI SACHIKO , KOTANI TOSHIYA , TANAKA SATOSHI , WATANABE SUSUMU , YANO MITSUHIRO
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , G03F7/20 , G06F17/50 , H01L21/027 , G03F1/08
摘要： PROBLEM TO BE SOLVED: To correct a design pattern to a shape suited to mask plotting or inspection by simple processing. SOLUTION: In a pattern correcting method to be executed by a computer, 1st correction for sides satisfying a prescribed condition out of sides constituting a designed pattern is performed by calculating correction values obtained considering an optical proximity effect. Then 2nd correction for sides not satisfying the prescribed condition is performed by using the correction value of the side adjacent to the side not satisfying the prescribed condition out of the sides corrected by the 1st correction and the sides corrected by the 1st correction are connected to each other with a segment. COPYRIGHT: (C)2003,JPO

20. 发明专利

JP2003017390A Pattern forming method and mask used for pattern formation 审中-公开
标题翻译：用于图案形成的图案形成方法和掩模
公开(公告)号：JP2003017390A
公开(公告)日：2003-01-17
申请号：JP2001199647
申请日：2001-06-29
申请人： Toshiba Corp , 株式会社東芝
发明人： KOTANI TOSHIYA , TANAKA SATOSHI , INOUE SOICHI
IPC分类号： G03F1/00 , G03F1/36 , G03F1/68 , G03F1/70 , G03F7/20 , H01L21/027 , H01L21/302 , H01L21/3065 , G03F1/08
CPC分类号： G03F1/36 , Y10S438/926
摘要： PROBLEM TO BE SOLVED: To correct size variation of an isolated pattern resulting from an etching process.
SOLUTION: A method includes a stage where a permissible value of an etching conversion difference is determined and the maximum distance X
max between patterns corresponding to the determined etching conversion difference is found, a stage where a design layout is generated by arranging gate patterns so that the distance XG
- G between gate patterns is less than the maximum distance X
max or arranging a gate pattern and a dummy pattern so that the distance XG
- D between the gate pattern and dummy pattern is less than the maximum distance X
max , a stage where design data of a mask are converted according to the design layout, and a stage where a gate pattern is formed by lithography and etching by using the converted design data.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：校正由蚀刻工艺产生的隔离图案的尺寸变化。解决方案：一种方法包括确定蚀刻转换差的容许值并找到与所确定的蚀刻转换差相对应的图案之间的最大距离Xmax的阶段，其中通过布置栅极图案产生设计布局，使得栅极图案之间的距离XG-G小于最大距离Xmax或排列栅极图案和虚设图案，使得栅极图案和虚拟图案之间的距离XG-D小于最大距离Xmax，设计数据根据设计布局转换掩模，并且通过使用转换的设计数据通过光刻和蚀刻形成栅极图案的阶段。

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