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    • 14. 发明专利
    • FEED APPARATUS OF ELECTRONIC COMPONENT
    • JPH07170093A
    • 1995-07-04
    • JP31460993
    • 1993-12-15
    • SONY CORP
    • ISOBE AKIRAOKUDA HIROYUKI
    • B23P19/00H05K13/02
    • PURPOSE:To obtain the feed apparatus which can increase the feed efficiency of a component, whose cost can be lowered and which can be miniaturized. CONSTITUTION:The feed apparatus is provided with a conveyance duct 21 and pressure member 37 which divide many chip-electronic-component aggregates 27 into chip resistors 26 and with a nozzle 38 by which the individual resistors 26 divided by the members are mounted on a board for circuit formation. As a result, the many chip-electronic-component aggregates 27 can be fed continuously and divided into the chip resistors 26, and the individual resistors 26 which have been divided can be mounted on the board for circuit formation by means of the nozzle 38. As a result, it is not required to stop the drive of the feed apparatus when components are fed. In addition, since the chip-electronic- component aggregates 27 are used so as to feed electronic components, a material is not wasted, and a cassette mounting space in conventional cases is made inessential.
    • 17. 发明专利
    • VIDEO SIGNAL MEASURING INSTRUMENT
    • JPS63204894A
    • 1988-08-24
    • JP3621487
    • 1987-02-19
    • SONY CORP
    • OKUDA HIROYUKINARITA ATSUO
    • H04N17/06
    • PURPOSE:To eliminate the influence of a skew (time base discontinuity) occurring at the time of head-switching and to always generate stable sampling clock suitable for data-digitization by obtaining a sampling clock from a PLL circuit. CONSTITUTION:A horizontal synchronizing signal separated from a video signal is supplied to a PLL circuit 13 via gate means 33, 34. The means 33, 34 are controlled by a deciding means 35 that discriminates the propriety of the horizontal synchronizing signal. If the horizontal synchronizing signal is normal, the gate means 33, 34 are opened to supply the signal to the PLL circuit 13, but if abnormal, the gate means 33, 34 are closed to interrupt the supply to the circuit 13. In a skew correction means 11, a gate signal is generated in the vicinity of a skew-occurring point in response to a vertical synchronizing signal, and a normal horizontal synchronizing signal is made pass by this gate signal to reset the frequency divider 12b of the PLL circuit 13. As a result, the stable sampling clock can be always obtained.