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    • 12. 发明专利
    • PROTECTIVE DEVICE AGAINST OVERCURRENT
    • JPH1168042A
    • 1999-03-09
    • JP22939097
    • 1997-08-26
    • ROHM CO LTD
    • HIGASHIDA YOSHIFUMI
    • H01L27/04H01L21/822
    • PROBLEM TO BE SOLVED: To obtain a protective device, against an overcurrent, whose structure is simple and which can be used semipermanently by a method wherein a second current passage can be formed in parallel with a first current passage in a semiconductor layer and a current-passage formation layer which comprises a resistance component is formed on the semiconductor layer via an insulating film. SOLUTION: A current-passage formation layer 1 is formed, via an insulating film 2, on a semiconductor layer 1 in which a first current passage 5 can be formed, it can form a second current passage 6 in parallel with the first current passage 5 in the semiconductor layer 1, and it comprises a resistance component. A connection means 7 electrically connects one end part of the first current passage 5 to one end part of the second current passage 6 in such a way that the first current passage 5 and the second current passage 6 are connected in series. In addition, an output terminal 5a and an input terminal 6a are installed in such a way that a current source can be connected across the other end part of the first current passage 5 and the other end part of the second current passage 6. In this manner, the current-passage formation layer 3 which comprises a resistance component is formed on the semiconductor layer 1 via the insulating film 2.
    • 14. 发明专利
    • SEMICONDUCTOR DEVICE
    • JPH09252119A
    • 1997-09-22
    • JP5904396
    • 1996-03-15
    • ROHM CO LTD
    • HIGASHIDA YOSHIFUMI
    • H01L29/78
    • PROBLEM TO BE SOLVED: To provide a semiconductor device of OSFET, UGBT and the like, which has structure where a gate finger extending from a gate electrode pad is eliminated and can uniformly apply gate voltage to the gate electrodes of respective unit cells. SOLUTION: The semiconductor device has a first conductive low impurity intensity layer 2 formed on a semiconductor substrate 1 acting as a common drain area, second conductive well areas 3 which are independently arranged in a matrix form in rows and columns that are selectively formed on the surface part of the low impurity intensity layer 2, first conductive source areas 4 formed in a circle on the surface in the well areas 3, source electrodes 8 which are brought into contact with the well areas 3 and the source areas 4 in common, and the gate electrodes 6 provided through gate insulating films 5 so that they cover the spaces between the well areas 3. The gate electrode pad 6 is formed on the insulating films 18 formed on the source electrodes 8, and it is electrically connected with the gate electrodes 6 through openings 17 formed in the insulating film 18.
    • 15. 发明专利
    • VERTICAL MOSFET
    • JPH09121047A
    • 1997-05-06
    • JP27596795
    • 1995-10-24
    • ROHM CO LTD
    • HIGASHIDA YOSHIFUMI
    • H01L29/06H01L29/78
    • PROBLEM TO BE SOLVED: To minimize an inactive area by rotating the source areas adjacent to each other on the surfacial layer of a substrate which forms a common drain area and arranging them in matrix. SOLUTION: An n type epitaxial layer 2 for a common drain area is formed on a semiconductor substrate, and a square P type well 3 is arranged in matrix on the surfacial layer thereof. A square, circular source area 4a is formed in a manner that its respective sides are parallel to the arrangement direction, while source areas 4b, 4c, 4d, and 4e are square and circular and the area 4a rotated at 40 deg. is arranged thereagainst. A current flows not only in the adjoinging source areas but in an area surrounded with four source area, so that the surfacial area of the layer 2 for a drain area can be utilized as far as possible as a current route. Therefore, a vertical MOSFET can reduce the area rate of the inactive area, resulting in minimization of ON-state resistance.
    • 18. 发明专利
    • Junction field-effect transistor and manufacturing method therefor
    • 连接场效应晶体管及其制造方法
    • JP2008066619A
    • 2008-03-21
    • JP2006245110
    • 2006-09-11
    • Rohm Co Ltdローム株式会社
    • HIGASHIDA YOSHIFUMI
    • H01L29/80H01L21/337H01L29/808
    • PROBLEM TO BE SOLVED: To provide a junction field-effect transistor which is reduced in planar size, and to provide a manufacturing method therefor.
      SOLUTION: The junction field-effect transistor 1 has an n
      - -type epitaxial layer 3 laminated on a semiconductor substrate 2. The n
      - -type epitaxial layer 3 has a plurality of gate regions 4 formed separated at intervals, and also has source regions 6 formed between adjacent gate regions 4 separated at intervals among these gate regions 4. Intervals of deep portions of the adjacent gate regions 4 are narrower than intervals of surface layer portions thereof. Gate electrodes 5 and source electrodes 7 are connected to the gate regions 4 and the source regions 6. A drain electrode 8 is connected to the reverse side of the semiconductor substrate 2.
      COPYRIGHT: (C)2008,JPO&INPIT
    • 要解决的问题:提供减小平面尺寸的结型场效应晶体管,并提供其制造方法。 结型场效应晶体管1具有层叠在半导体衬底2上的n - SP>型外延层3。 具有形成为间隔隔开的多个栅极区域4,并且还具有形成在这些栅极区域4之间间隔开的相邻栅极区域4之间的源极区域6.相邻栅极区域4的深部分的间隔比表面层的间隔窄 部分。 栅电极5和源电极7连接到栅极区域4和源极区域6.漏极电极8连接到半导体衬底2的背面。(C)2008,JPO和INPIT