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11. 发明专利

JP2017079324A 半導体装置および半導体装置の製造方法审中-公开
公开(公告)号：JP2017079324A
公开(公告)日：2017-04-27
申请号：JP2016111758
申请日：2016-06-03
申请人：富士電機株式会社 , Fuji Electric Co Ltd
发明人： SHIIKI TAKASHI , YAMADA SHOJI , HARADA YUICHI , HOSHI YASUYUKI
IPC分类号： H01L29/78 , H01L21/329 , H01L21/336 , H01L21/76 , H01L29/12 , H01L29/861 , H01L29/866 , H01L29/868
摘要：【課題】高温度条件下においても信頼性の高い半導体装置および半導体装置の製造方法を提供すること。【解決手段】メイン半導体素子10と同一の炭化珪素基体100に、過電圧保護部、電流センス部および温度センス部等の保護・制御回路が配置されている。メイン半導体素子10のゲートパッド19、保護・制御回路を構成する複数の半導体素子の各電極パッド32,48,54,55は、活性領域101の中央部に直線状に1列に配置されている。メイン半導体素子10のソースパッド12は、ソースパッド12以外の電極パッド19,32,48,54,55を挟み込むように複数配置されている。メイン半導体素子10のソースパッド12およびゲートパッド19と、保護・制御回路を構成する複数の半導体素子の各電極パッド32,48,54,55には、すべてめっき膜および半田膜を介して端子ピンが配置されている。【選択図】図4

12. 发明专利

JP2017079225A 半導体装置および半導体装置の製造方法审中-公开
公开(公告)号：JP2017079225A
公开(公告)日：2017-04-27
申请号：JP2015205336
申请日：2015-10-19
申请人：富士電機株式会社 , Fuji Electric Co Ltd
发明人： HOSHI YASUYUKI , HARADA YUICHI , SHIIKI TAKASHI
IPC分类号： H01L29/78 , H01L21/3205 , H01L21/336 , H01L21/768 , H01L23/522 , H01L29/12
CPC分类号： H01L29/1608 , H01L21/02529 , H01L21/76895 , H01L21/823807 , H01L23/535 , H01L24/26 , H01L27/092 , H01L29/0649 , H01L29/2003 , H01L29/36 , H01L29/66712 , H01L29/7805 , H01L29/8611
摘要：【課題】ピン状電極を半田で接合した半導体装置の信頼性を向上させる。【解決手段】半導体装置は、第1導電型のワイドバンドギャップ半導体基板1と、第1導電型のワイドバンドギャップ半導体堆積層2と、第2導電型半導体領域10と、第2導電型のワイドバンドギャップ半導体層11と、第1の第1導電型領域12と、第2の第1導電型領域4と、を備え、半導体装置のソース電極8上のめっき膜16の幅wは、10μm以上であり、めっき膜16の下部、第2導電型半導体領域10の表面にワイドバンドギャップ半導体層11が設けられる。【選択図】図1

13. 发明专利

JP2017092368A 半導体装置および半導体装置の製造方法审中-公开
公开(公告)号：JP2017092368A
公开(公告)日：2017-05-25
申请号：JP2015223774
申请日：2015-11-16
申请人：富士電機株式会社 , Fuji Electric Co Ltd
发明人： HOSHI YASUYUKI
IPC分类号： H01L29/78 , H01L21/336 , H01L29/06 , H01L29/12
CPC分类号： H01L29/7813 , H01L21/02378 , H01L21/02529 , H01L21/02634 , H01L29/0865 , H01L29/1079 , H01L29/1608 , H01L29/36 , H01L29/41741 , H01L29/4236 , H01L29/66068 , H01L29/66666 , H01L29/66734 , H01L29/7827
摘要：【課題】簡易に形成することができ、活性部の耐電圧を抑えることにより耐圧構造部の耐電圧設計を容易にし、かつオン抵抗を下げる。【解決手段】炭化珪素半導体基体の第1主面側には、トレンチ16、n+型高濃度領域5が設けられ、n+型高濃度領域5の内部に、p型ベース層6に接する第1p+型ベース領域3を囲む、n+型高濃度領域5より高不純物濃度の第3n型領域20と、トレンチ16の底部に設けられた第2p+型ベース領域4を囲む、n+型高濃度領域5より高不純物濃度の第4n型領域21とが設けられる。【選択図】図1

14. 发明专利

JPH07130999A INSULATED-GATE BIPOLAR TRANSISTOR 失效
公开(公告)号：JPH07130999A
公开(公告)日：1995-05-19
申请号：JP27471193
申请日：1993-11-04
申请人： FUJI ELECTRIC CO LTD
发明人： HOSHI YASUYUKI , FUJISHIMA NAOTO , KASHIMA MASAHITO , SHIMABUKURO HIROSHI
IPC分类号： H01L29/78 , H01L29/739
摘要： PURPOSE:To reduce a transient loss, a steady loss and a switching loss which are increased due to a high frequency by a method wherein a lateral bipolar transistor is constituted on the surface layer on the side of an emitter for a vertical insulatedgate bipolar transistor and an electrode on the other side is connected to a collector electrode. CONSTITUTION:Only an n-layer 21 is formed on the surface layer of an n layer 1, and an extraction electrode 13 is brought into contact with it. Other parts of an electron current which has flowed into the n layer 1 at a time when an element is turned on are passed through the lower part of an insulating layer 52 from a part directly under a gate oxide film 5, and they flow into the n-layer 21 whose potential is identical to that of a collector electrode 10. That is to say, a lateral-direction insulated-gate bipolar transistor which is formed of an emitter electrode 7, an n emitter layer 3, a p-base layer 2, the gate oxide film 5, a gate electrode 6, the n layer 1, the n-layer 21 and the extraction electrode 13 is connected in parallel with a vertical-direction spnp transistor. Thereby, the operation of a space bipolar transistor is reinforced, and carriers can be pulled out usefully in a turning-off operation.

15. 发明专利

JPH04248363A POWER SOURCE CIRCUIT USING CONDUCTIVITY MODULATING MOSFET 失效
公开(公告)号：JPH04248363A
公开(公告)日：1992-09-03
申请号：JP732791
申请日：1991-01-25
申请人： FUJI ELECTRIC CO LTD
发明人： HOSHI YASUYUKI
IPC分类号： H02M3/28 , H04N5/63
摘要： PURPOSE:To prevent the occurrence of noise by ringing distortion by connecting a capacitor and a resistor in parallel between the gate and the emitter of a conductivity modulating MOSFET (GBT), and lowering the annihilation speed of the remaining carriers of the IGBT. CONSTITUTION:An input resistor 5 and an input capacitor 6 are connected in parallel to the gate input part of a switching transistor IGBT 2. Hereupon, the value of the input capacitor 6 is not more than 100OpF, and the value of an input resistor 5 is 1kOMEGA. Accordingly, the speed when discharging the charge of the gate is weakened when the IFGT 2 is turned off. Moreover, at the same time, the discharge of the charge within the chip area is performed smoothly without change, and the sudden current drop of a collector current at the time of turning off the gate is lightened, and the IGBT 2 is turned off without increasing the loss in generation of the IGBT 2.

16. 发明专利

JPH04212464A HORIZONTAL CONDUCTIVITY MODULATION TYPE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04212464A
公开(公告)日：1992-08-04
申请号：JP3485891
申请日：1991-03-01
申请人： FUJI ELECTRIC CO LTD
发明人： HOSHI YASUYUKI
IPC分类号： H01L29/68 , H01L29/739 , H01L29/78
摘要： PURPOSE:To lower the ON voltage for cutting down the turn off time by a method wherein a sub-emitter electrode is provided even in a first conductivity type first layer beneath a second conductivity type second layer on the emitter electrode and collector electrode side in the RESURE structure to be connected to the emitter electrode. CONSTITUTION:A substrate emitter electrode (sub-emitter electrode) 14 in contact with the rear surface of a P substrate 1 is provided to be shortcircuited with an emitter electrode 12. That is, a terminal G, a terminal E1, a terminal C1 and a terminal E2 are respectively connected to a gate electrode 6, an emitter electrode 12, a collector electrode 13 and an emitter electrode 14. On the other hand, by impressing emitter electrodes with voltage, the electron current runs in from an n emitter region 4 to an n layer 2 and an n buffer region 8 passing through a channel region 7. Through these procedures, the potential declines by P /n between a P collection region 9 and the n buffer region 8 so that the conductivity may be modulated in the n buffer region 8 by hole injection from the P collector region 9.

17. 发明专利

JPH08274303A INSULATED GATE THYRISTOR 失效
公开(公告)号：JPH08274303A
公开(公告)日：1996-10-18
申请号：JP7853095
申请日：1995-04-04
申请人： FUJI ELECTRIC CO LTD
发明人： HOSHI YASUYUKI
IPC分类号： H01L29/74 , H01L29/739 , H01L29/749 , H01L29/78
摘要： PURPOSE: To improve the correlation between the on-voltage and the turn-off loss by providing an anode short-circuiting construction which short-circuits an anode-side (p) emitter layer partially. CONSTITUTION: A p-type base region 2 is selectively formed on an n substrate 1, and besides a p region 3 is selectively formed. In the p region 3 an n-type source region 5 and an n-type floating region 15 are selectively formed simultaneously. A gate oxide film 6 is selectively formed on the surfaces of the n substrate 1 and the p-type base region 2, and a gate electrode 7 is formed on the surface of the gate oxide film 6. On the upper part an insulating film 8 is formed so as not to cover the whole surface of the n-type floating region 15 leaving a part of the surface of the n-type source region 5. A resistor 9 is selectively formed on the surfaces of the p-type base region 2, p region 4, and the insulating film 8, and a protective film 10 is selectively formed on the surface of the resistor 9, and on the upper exposed surface a cathode electrode is formed. On the other surface of the n substrate 1 p-type emitter regions 121 are formed selectively.

18. 发明专利

JPH08236543A MANUFACTURE OF INSULATED-GATE TYPE THYRISTOR 失效
公开(公告)号：JPH08236543A
公开(公告)日：1996-09-13
申请号：JP3484695
申请日：1995-02-23
申请人： FUJI ELECTRIC CO LTD
发明人： HOSHI YASUYUKI
IPC分类号： H01L29/74 , H01L21/265 , H01L21/332 , H01L21/8234 , H01L27/088 , H01L29/739 , H01L29/749 , H01L29/78
摘要： PURPOSE: To shorten the production process of an insulatedgate type thyristor by a method wherein a photolithography process for forming second p regions is omitted and the formation of these regions and the introduction of second conductivity type impurities into a second polysilicon film are conducted by merely changing an accelerating voltage for the ion-implantation. CONSTITUTION: A gate oxide film 4 and a gate polysilicon film 5 are laminated on the surface of an n-type layer 1, p-type impurities are ion-implanted through an aperture to form p-type regions 2, then, n-type regions 3 are formed of an arsenic film and thereafter, a PSG film 6 is deposited, this film 6 is selectively removed, a polysilicon film 8 for resistance is formed on the film 6, boron having a dose less than that of the film 5 is ion-implanted in this film 8 and regions 7 are formed simultaneously with the ion-implantation. Moreover, the film 8 is selectively removed to form an oxide film 9 on the film 8, an opening is formed in the film 9 so that the film 8 is exposed, the upper part of the film 9 is covered with an Al-Si film and an emitter electrode 10 is formed.

19. 发明专利

JPH05335328A 失效
公开(公告)号：JPH05335328A
公开(公告)日：1993-12-17
申请号：JP14184792
申请日：1992-06-03
申请人： FUJI ELECTRIC CO LTD
发明人： HOSHI YASUYUKI
IPC分类号： H01L21/8222 , H01L21/331 , H01L27/082 , H01L29/73 , H01L29/732
摘要： PURPOSE:To enable voltage-driving of a Darlington transistor where the base of one bipolar transistor is connected to the emitter of another bipolar transistor. CONSTITUTION:On a semiconductor substrate, a source area 43 is formed in a base region 31 of the bipolar transistor on the front stage formed together with the band gap transistor on the rear stage, and a channel 81 is formed on the surface layer of base region sandwiched between the source region 43 and a common collector region. A MOS structure is thus provided and it supplies the front stage transistor with base current. Or, an the substrate surface on which such cascade-connected MOSFET and bipolar transistor are farmed, a rear stage transistor formed by laminating a base layer and emitter layer is formed, and on top of that, a vertical MOSFET in which the emitter layer serves as a drain is formed, and in addition, gate electrodes 91 are connected to each other for faster turn-off.

20. 发明专利

JPH0529628A INSULATING-GATE TYPE BIPOLAR TRANSISTOR 失效
公开(公告)号：JPH0529628A
公开(公告)日：1993-02-05
申请号：JP17854891
申请日：1991-07-19
申请人： FUJI ELECTRIC CO LTD
发明人： HOSHI YASUYUKI
IPC分类号： H01L29/78 , H01L29/08 , H01L29/739
摘要： PURPOSE:To make the narrowing of a carrier path caused by a JEFT effect small and to decrease ON voltage by increasing the impurity concentration of a surface layer which is thicker than the depth of the base region of a first layer, thereby suppressing the expansion of a depletion layer from a part which is continued to the bottom surface of the base region and has the large curvature. CONSTITUTION:As a p plate 10, a silicon substrate having the specific resistance of 0.01OMEGAcm is used. An N buffer layer 9 having the specific resistance of 0.01OMEGAcm is laminated thereon to the thickness of 5mum. An N high-specific-resistance layer 1 having the specific resistance of 2-200OMEGAcm is laminated to the thickness of 50mum. An N low-specific-resistance surface layer 21 having the specific resistance of 2-60OMEGAcm is laminated to the thickness of 5mum. These layers are sequentially laminated by epitaxial growing. A gate electrode 6 is formed on the surface of the N layer 21 through a gate insulating film 5. Ions are implanted with the gate electrode as a mask. A p-type base region 2 and an N emitter region 3 are formed by heat treatment. Thus, the expansion of a depletion layer at the outside of a part which is continued to the bottom surface of the p-type base region and has the large curvature is suppressed. The width of a part between the p-type base regions 2 can be shortened.

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