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11. 发明专利

JPH03187547A PACKET SWITCH 失效
公开(公告)号：JPH03187547A
公开(公告)日：1991-08-15
申请号：JP32689589
申请日：1989-12-15
申请人： NEC CORP
发明人： AKATA MASAO
IPC分类号： H04L12/931
摘要： PURPOSE:To reduce an influence caused by a packet, which previously arrives and waits for an outgoing line, and to improve throughput by calculating minimum time for an output to the outgoing line when the packet arrives at a packet buffer. CONSTITUTION:When the packets arrives from incoming lines 101-10n at packet buffers 201-20n, a packet transmission request is outputted through a packet transmission request bus 6 to a time slot schedule device 9. The time slot schedule device 9 notifies the earliest time through a packet transmission time return bus 7 to each packet buffer so that the packet requesting the transmission can be outputted without colliding in the outgoing line. Thus, when the packet is sent out, the arbitration can be executed without fail and the throughput of a space switch 4 can be improved.

12. 发明专利

JPH02192324A SUBSCRIBER LINE TERMINAL CIRCUIT 失效
公开(公告)号：JPH02192324A
公开(公告)日：1990-07-30
申请号：JP1130389
申请日：1989-01-20
申请人： NEC CORP
发明人： AKATA MASAO
IPC分类号： H04B3/03 , H04Q3/42
摘要： PURPOSE:To prevent the S/N of a transmission path and a noise in radio communication from being deteriorated and to dispense with echo suppression by an analog adder by providing a second feedback path as an echo signal suppression path consisting of a resistor and a capacitor. CONSTITUTION:A signal voltage between two-wire subscriber line terminals 1 and 2 is outputted to a four-wire output terminal 8 via a bypass filter consisting of a two-wire signal voltage detection circuit 3, an operational amplifier 6, the capacitor C, and the resistors R1 and R2. Also, a reception signal inputted from a four-wire input terminal 9 supplies a signal current between the terminals 1 and 2 by an inversion amplifier consisting of an operational amplifier 7 and the resistors R3 and R4 and a two-wire signal driving circuit 4. The second feedback path as the echo signal suppression path consisting of the resistor R6 and the capacitor C2 is provided. In such a way, the echo component -1/2VR of the output of the amplifier 7 and the reception signal component 1/2VR of the output of the circuit 3 are offset by an adder circuit consisting of the amplifier 6, the resistors R1, R2, and R3, and the capacitors C1 and C2, which prevents the S/N of the transmission path and the noise in the radio communication from being deteriorated.

13. 发明专利

JPS6130860A Control system of charging pulse transmission 失效
标题翻译：充电脉冲传输控制系统
公开(公告)号：JPS6130860A
公开(公告)日：1986-02-13
申请号：JP15256284
申请日：1984-07-23
申请人： Nec Corp
发明人： ASAKURA JUNJI , AKATA MASAO
IPC分类号： H04M15/00 , H04M15/28
CPC分类号： H04M15/28
摘要： PURPOSE:To decrease the processing time of a central controller by providing a control means to transmit a charging pulse to subscriber's equipment into a subscriber circuit intalled corresponding to each subscriber line in a telephone exchange. CONSTITUTION:The subscriber circuit 11 installed in correspondence to each subscriber line 5 has a talking current supply circuit 2 or the like. A central controller 4 decides the charging pulse period based on a connection destination of a call from the subscriber's equipment detected by a loop supevisory circuit 3 and transmits it to a charging pulse period generating circuit 10. Since the circuit 10 drives a normal/reverse polarity switching circuit 1 and the circuit 3 via a changing pulse waveform control timing generating circuit 8 at each pulse period, the call number is stored in a charging call storage memory 9 together with a changing pulse transmitted to the subscriber's equipment. Then the central controller 4 does not require timing generation processing, the processing time is reduced.
摘要翻译：目的：通过提供控制装置来减少中央控制器的处理时间，以便将用户设备的充电脉冲发送到与电话交换机中的每个用户线对应的用户电路中。构成：对应于每个用户线路5安装的用户电路11具有通话电流供应电路2等。中央控制器4基于由循环监视电路3检测到的来自用户设备的呼叫的连接目的地来确定充电脉冲周期，并将其发送到充电脉冲周期发生电路10.由于电路10驱动正常/反向极性开关电路1和电路3经由变化脉冲波形控制定时发生电路8在每个脉冲周期，将呼叫号码与发送到用户设备的改变脉冲一起存储在计费呼叫存储存储器9中。然后中央控制器4不需要定时生成处理，处理时间减少。

14. 发明专利

JP2001044979A CLOCK DISTRIBUTION CIRCUIT 失效
公开(公告)号：JP2001044979A
公开(公告)日：2001-02-16
申请号：JP21071999
申请日：1999-07-26
申请人： NEC CORP
发明人： AKATA MASAO
IPC分类号： G06F1/06 , H03K5/00 , H03L7/093 , H03L7/22 , H04J3/00 , H04J3/06 , H04L7/033
摘要： PROBLEM TO BE SOLVED: To assure an internal operation of a device when a switching instruction of a reference clock is given from the outside by using a limiting means which limits the highest phase varying speed to set the highest phase varying speed of a phase locked loop(PLL) circuit of every stage at a level higher than that of the PLL circuit of the preceding stage. SOLUTION: In a PLL 0 (12), a voltage controlled oscillator(VCO) input voltage limiting circuit 25 is placed between a loop filter 22 and a VCO 23. When the voltage-frequency characteristic of the VCO 23 used by the PLL 0 (12) is almost equal to that used by a PLL 1 (13), the VCO input voltage range of the PLL 0 (12) is limited by the input voltage limiting circuit 25. Thus, it is assured that the phase variance of the PLL 1 (13) is faster than that of the PLL 0 (12) even when the switching is performed between the clock sources 15 and 16 and the VCO input voltage has a large change. Thus, the circuit 25 can assure that the highest phase varying speed of a PLL of every stage is higher than that of the PLL of the preceding stage.

15. 发明专利

JPH05304459A 失效
公开(公告)号：JPH05304459A
公开(公告)日：1993-11-16
申请号：JP28263192
申请日：1992-10-21
申请人： NEC CORP
发明人： AKATA MASAO
IPC分类号： H03K19/0175 , H04L25/02
摘要： PURPOSE:To prevent a CMOS level from being unfixed even when a pseudo ECL input becomes open in a logical level converting circuit from the pseudo ECL level to the CMOS level. CONSTITUTION:The circuit is constituted in such a way that the terminating circuit of a pseudo ECL signal is serially connected to terminating resistors Rt1 and Rt2 so as to connected to a negative power source Vee and the resistor Rt2 is connected to a capacitor Ct in parallel. Thus, when the pseudo ECL level signal input becomes open, a fixation is executed in the potential of the negative power source Vee and the output of AMP 3 executing conversion into a CMOS level is fixed to logical '0'.

16. 发明专利

JPH04165815A INPUT BUFFER CIRUCIT 失效
公开(公告)号：JPH04165815A
公开(公告)日：1992-06-11
申请号：JP29285890
申请日：1990-10-30
申请人： NEC CORP
发明人： AKATA MASAO
IPC分类号： H03K5/02 , H03K19/0185
摘要： PURPOSE:To make an applied area a wide range by combiningly providing plural sub input buffer circuits corresponding to a different threshold voltage level, and a threshold voltage selecting circuit properly selecting the plural sub input buffer circuit by a control signal introduced from an outside and making to correspond to the different threshold voltage. CONSTITUTION:In case an L(low) level control signal is inputted to a control input terminal 52, the threshold voltage, corresponding to an input terminal 51 is set by the current driving capacity ratio of a PMOS transistor 4 to an NMOS transistor 3. And in case an H(high) level control signal is inputted to the control input terminal 52, since it becomes a pull-down construction by NMOS transistors 1, 2 and 3, the threshold voltage is set lower than a time when the control input signal is the L level. Therefore, by setting the sizes of the PMOS transistor 4 and the NMOS transistors 1, 2 and 3 appropriately, the both threshold voltages of a CMOS level threshold voltage (2.5V) and a TT level threshold voltage (1.4V) are selected optionally.

17. 发明专利

JPH05137167A TIME SWITCH 失效
公开(公告)号：JPH05137167A
公开(公告)日：1993-06-01
申请号：JP32152291
申请日：1991-11-11
申请人： NEC CORP
发明人： AKATA MASAO
IPC分类号： H04Q3/52 , H04Q11/04
摘要： PURPOSE:To realize a large-capacity time switch by converting a highway to a multiframe highway to extend the time slot time assigned to one channel. CONSTITUTION:An input highway 11 is converted to a first multiframe highway 14 by a multiframe conversion circuit 13. Two frames constitute one multiframe. With respect to the highway format of the highway 14, two time slot times (2T) of the input highway are one time slot time. This highway 14 is inputted to a time switch 15, which is operated by a multiframe pulse MFP of one period, with the period of a frame pulse signal FP2. This time switch 15 is switched for the highway 14 at intervals of 2T. The sequence of 0 time slot is switched to that of two time slots and is outputted to a second multiframe highway 16. This highway 16 is converted to a highway of one frame period by a multiframe inverse conversion circuit 17 and is outputted as an output highway 12.

18. 发明专利

JPH04263510A FLIP-FLOP CIRCUIT 失效
公开(公告)号：JPH04263510A
公开(公告)日：1992-09-18
申请号：JP4593491
申请日：1991-02-18
申请人： NEC CORP
发明人： AKATA MASAO
IPC分类号： H03K3/012 , H03K3/037 , H03K3/3562
摘要： PURPOSE:To prevent set-up time from being prolonged by an influence to a master latch due to the state of a slave latch. CONSTITUTION:While a clock C is logic '0', MOS transfer gates MP0 and NM0 are turned on, and data from a data input terminal D is fetched through an inverter INV 0 into the inside of the latch. When the clock C is turned to logic '1', MOS transfer gates (MP1 and MN1) are turned on, and the data is held by a positive feedback loop composed of the INV 1 and a gate NAND 0. The data is transmitted to the slave latch with an INV 2 as a buffer circuit, and the data is fetched into the match by turning on MOS transfer gates (MP2 and MN2) while the clock input C is logic '1'. While the clock C is logic '0', MOS transfer gates (MP3 and MN3) are turned on, and the data is held by a positive feedback loop composed of an INV 3 and a gate NAND 1. An output to a data output terminal Q is taken out from the preceding step of the INV 3 through an INV 4 so as to match a logic polarity with the data input terminal D.

19. 发明专利

JPH04172816A LEVEL CONVERSION CIRCUIT 失效
公开(公告)号：JPH04172816A
公开(公告)日：1992-06-19
申请号：JP30218590
申请日：1990-11-07
申请人： NEC CORP
发明人： AKATA MASAO
IPC分类号： H03K19/0175
摘要： PURPOSE:To perform CMOS/ECL level conversion by performing level shifting and by using a diode to prevent the base potential of an output bipolar transistor from becoming too low. CONSTITUTION:When a high level is impressed upon an input terminal VIN, a MOS transistor M2 is turned on and the base charge of a bipolar transistor Q1 is extracted through diodes D1-D4 and the transistor M2. When the base charge is extracted, the base potential of the transistor Q1 is dropped to VSS+4 Vf by means of the diodes D1-D4. Accordingly, the VBE of the transistor is not excessively reverse-biased. When the base charge is extracted and the electric current disappears, diodes D7 and D8 are turned on and suppress the potential drop. Therefore, the occurrence of an excessive reverse-biased state can be evaded and CMOS/ECL level conversion can be performed with small power consumption.

20. 发明专利

JPH03235411A LATCH CIRCUIT AND FLIP FLOP CIRCUIT 失效
公开(公告)号：JPH03235411A
公开(公告)日：1991-10-21
申请号：JP3076290
申请日：1990-02-09
申请人： NEC CORP
发明人： AKATA MASAO , WAKASUGI SHINJI
IPC分类号： H03K3/037
摘要： PURPOSE:To make an inverter to generate an opposite phase phi from a clock phiunnecessary, and to reduce power consumption by substituting one input sampling MOS transistor(TR) for an input sampling transmission gate, and making a loop opening and closing transmission gate into one small TR. CONSTITUTION:This circuit is constituted of one input sampling P channel type MOS TR MPT, one latching inverter INV1, and a feedback circuit FB1 provided with a MOS TRs MPI, MN11, and an N channel type MOS TR MN12. When an input signal is in a high level, the potential of a node N1 becomes the potential potential-divided by the TRs MPT, MN11 and the impedance of a signal source, but an internal state is inverted by making previously the size of the TR MN11 small compared with the size of the TR MPT so that the value exceeds the threshold of INV1.

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