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11. 发明专利

JPS56110371A COMMUNICATION CONTROLLER 失效
公开(公告)号：JPS56110371A
公开(公告)日：1981-09-01
申请号：JP1238180
申请日：1980-02-06
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO
发明人： NAKAMURA YUKIO , ENDOU TAKENORI , SAITOU ISAO , YAMAUCHI HIDEO , INUI YOSHIO , DOI AKIHIKO
IPC分类号： H04L29/04 , G06F13/00 , H04L12/00 , H04L29/02
摘要： PURPOSE:To realize an application of one communication controller for two systems, by discriminating in correspondence to the lines for several data communication lines having different bit transmission sequence, but, other transmission control procedures are used in common, and then controlling the data communication lines by the bit transmission sequence of each line. CONSTITUTION:The 2-bit register group 61 is provided in correspondence to lines (#0-#N) to store the transmission/reception sequence. The 1st selector 1-SEL selects a register among the group 61 via the selection signal line 401 led from the communication control part CCU plus the output enable signal line 402. The 2nd selector 2-SEL has a structure of m+1 bits and selects the reversed or nonreversed value of the lower-rank bit of the memory address designation line 403 which designates the memory address of the buffer memory BM, and then delivers it as a lower-rank bit of the memory BM. At the same time, the line control part group 62 is provided in correspondence to the lines to perform a control by every line.

12. 发明专利

JPS54117644A LINE FAULT REPORTING SYSTEM 失效
公开(公告)号：JPS54117644A
公开(公告)日：1979-09-12
申请号：JP2465378
申请日：1978-03-03
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD
发明人： INUI YOSHIO , AMADA HIROYUKI , OZEKI TAKAAKI
IPC分类号： H04L29/14 , G06F13/00 , H04L13/00
摘要： PURPOSE:To improve the throughput of a communication system by causing a line control part to decide the restoration of the line at a flag detection time and receive and display a flag newly and causing an interface control part to detect the flag and report the normalcy of the line to a data channel unit. CONSTITUTION:When detecting anomaly occurrence, line control part 202 stops the receiving operation and writes an executing address at final address #n307 and sets information indicating an anomaly occurrence cause to line status #n305. Meanwhile, interface control part 200 reads line status #n305 in control part 202 and sends it to a data channel unit and reports that an anomaly has occurred in data block receiving. Next, control part 202 decides that the data line has restored its normalcy when the flag is detected. Then, control part 202 erases fault information of status #n305 and sets a flag receiving display newly, and control part 200 detects it and reports the normalcy of the line to the data channel unit. As a result, the throughput of the communication system can be improved.

13. 发明专利

JPS57124950A Duplicated bus connecting system 失效
标题翻译：复用总线连接系统
公开(公告)号：JPS57124950A
公开(公告)日：1982-08-04
申请号：JP1045381
申请日：1981-01-27
申请人： Fujitsu Ltd , Hitachi Ltd , Nec Corp , Nippon Telegr & Teleph Corp , Oki Electric Ind Co Ltd
发明人： KAWANOBE TADASHI , EBIHARA MAKOTO , INUI YOSHIO , AMANO YUTAKA , TAKAHASHI RIYOUICHI
IPC分类号： H04L1/22 , G06F11/18 , G06F13/00 , G06F13/40 , H04L12/40
CPC分类号： H04L12/40 , G06F13/4022
摘要： PURPOSE:To prevent system down caused by the failure of a bus transmission line, providing a duplicated bus transmission line. CONSTITUTION:An access device 11 selects either one of gate 101 and 102 through the instruction of a bus route control circuit 301 and transmits the transmission data to a bus transmission line 31 or 32 via an interface section 51 or 52. On the other hand, an access device 21 to be accessed receives the data on the bus transmission line 31 or 32 via an interface section 71 or 72 according to the instruction of a bus route control circuit 401, selects it with a gate 201 or 202, and fetches it in the device as a reception data. Thus, since there are two routes to connect an arbitrary access device and the access device to be accessed, the dererioration in the economy of device due to increase in the interface is prevented and the lowering in the system reliability can be avoided.
摘要翻译：目的：为了防止总线传输线路故障导致的系统故障，提供复制的总线传输线。构成：接入装置11通过总线路径控制电路301的指示选择门101,102中的任一个，经由接口部51或52将发送数据发送到总线传输线31或32。另一方面，要访问的访问装置21根据总线路径控制电路401的指令经由接口部分71或72在总线传输线31或32上接收数据，用门201或202选择它，并将其取出该设备作为接收数据。因此，由于存在连接任意访问装置和要访问的访问装置的两条路由，所以防止了由于界面增加引起的设备经济性的下降，并且可以避免系统可靠性的降低。

14. 发明专利

JPS57130149A SYSTEM FOR INTERRUPTION PROCESSING OF MICROPROGRAM CONTROL DEVICE 失效
公开(公告)号：JPS57130149A
公开(公告)日：1982-08-12
申请号：JP1617481
申请日：1981-02-05
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE
发明人： INUI YOSHIO , MASUDA ETSUO
IPC分类号： G06F9/22 , G06F9/48
摘要： PURPOSE:To make discrimination of an interrupt source with a microprogram unnecessary, by using the input selecting signal to a multiplexer, which selects interrupt sources, for generating the address of a control memory area corresponding to the interrupt source. CONSTITUTION:Various interrupt sources are generated from an initializing request circuit 1, a periodical processing request circuit 2, a transmission processing request circuit 3, a receiving processing request circuit 4, a request circuit 5 for a fault processing A, a request circuit 6 for a fault processing B, and a request circuit 7 for a fault processing C and are inputted to a multiplexer 37. The multiplexer 37 selects inputs in accordance with an output signal 39 of a counting circuit 38, and a selected signal is outputted as an interrupt signal 11 to a sequencer of a microprogram when an interruption inhibiting circuit 9 permits interruption. The output signal 39 from the counting circuit 38 is inputted to the sequencer of the microprogram and is used for generating the address of a microprogram corresponding to the interrupt.

15. 发明专利

JPS54115036A CONTROL SYSTEM FOR MICROPROGRAM 失效
公开(公告)号：JPS54115036A
公开(公告)日：1979-09-07
申请号：JP2341778
申请日：1978-02-28
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE
发明人： INUI YOSHIO , DOI AKIHIKO , AMADA HIROYUKI , YAMAUCHI EIOU
IPC分类号： G06F9/22 , G06F3/00 , G06F13/00 , G06F13/38 , G11C7/00
摘要： PURPOSE:To increase the processing ability, by constituting the system that the control processing to perform the data delivery to the line terminal unit and the data write-in operation to the buffer memory is made one machine cycle. CONSTITUTION:The data from the data channel unit DCH is inputted to the input and output data buffer 200. The logical operation section 201 makes the address on the buffer memory 203 to store the said data in one machine cycle. In the next one machine cycle, the logical operation secion 201 takes the reception data from the buffer 200 and inputs it to the data buffer 204. The buffer mrmory 203 stores the content to the designated address in the next machine cycle. In case of data delivery, the logical operation section 201 reads out data from the buffer memory, performs logical operation and the result is inputted to the data buffer. The line contol secion 205 initiates transmission in the next machine cycle. When the delivery operation is executed independently of the microprogram, the transmission can be made by one machine cycle.

16. 发明专利

JPS54115033A CONTROL SYSTEM FOR INPUT AND OUTPUT INTERFACE 失效
公开(公告)号：JPS54115033A
公开(公告)日：1979-09-07
申请号：JP2341978
申请日：1978-02-28
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE
发明人： DOI AKIHIKO , INUI YOSHIO , AMADA HIROYUKI , YAMADA SHIGEKI
IPC分类号： G06F13/42 , G06F3/00
摘要： PURPOSE:To speed up the input and output operation, by performing the delivery of out signal, reception and detection of in signal, and delivery of out signal depending on the in signal, with one mircoinstruction. CONSTITUTION:The register 20 consists of the memory field GI 21 designating the types of a plurality or one out of the in signal and the memory field FO 24 designating a plurality of types or one among the out signal, and FO 24 consists of FO1(22) and FO1(23). The content of FO2(23) is decoded with the decoder 3(42) of the selection circuit 40 from the out signal delivery timing signal 2 and the out signal corresponded is outputted to the data channel unit. After that, in response to the out signal, when in signal is received from the data channel unit, the judgement circuit 30 judges it if it is the signal designated with FI 21, and if the designated signal, the content of FO1(22) is decoded at the decoder 3(42) with the timing signal of the timing circuit 1(34) and the corresponded out signal is delivered.

17. 发明专利

JPS54115037A CONTROL SYSTEM FOR PROGRAM 失效
公开(公告)号：JPS54115037A
公开(公告)日：1979-09-07
申请号：JP2341878
申请日：1978-02-28
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE
发明人： DOI AKIHIKO , INUI YOSHIO , YAMAUCHI EIOU , YAMADA SHIGEKI
IPC分类号： G06F9/26 , G06F3/00 , G06F9/22 , G06F9/46 , G06F13/00 , G06F13/10
摘要： PURPOSE:To eanble to assign to the processing of the control sequence in high priority level and effective processing for waiting time, by constituting the system that the format of transit of processing between control sequences and its time can be selected and instructed in advance arbitrarily. CONSTITUTION:Two control sequences constituting the program to execute with the sequence control section 40, that is, the control sequence executing the signal transmission and reception with the data channel unit related to the interface control section and the operation section 30, and that performing signal transmission and reception with terminal line related to the line control section 20 and the operation section 30 are respectively taken as F-CTL and L-CTL. At the processing transaction from F-CTL to L-CTL, the format of processing restoration from L-CTL to F-CTL with the display element from the sequence control section 40, that is, the selection of the restoration with the interrupt signal caused in arbitrary time or automatic restoration at the time reaching of the executed position of L-CTL to a point, can easily and efficiently perform the program processing.

18. 发明专利

JPS5941345B2 JPS5941345B2 - 失效
公开(公告)号：JPS5941345B2
公开(公告)日：1984-10-06
申请号：JP5030977
申请日：1977-04-30
申请人： Nippon Electric Co
发明人： INUI YOSHIO , KAWAI OSAMU
IPC分类号： H04M3/22 , H04Q3/545
CPC分类号： H04M3/22

19. 发明专利

JPS60102045A CONTROLLER OF MULTIPLE ADDRESS COMMUNICATION 失效
公开(公告)号：JPS60102045A
公开(公告)日：1985-06-06
申请号：JP21033383
申请日：1983-11-09
申请人： NIPPON ELECTRIC CO
发明人： INUI YOSHIO
IPC分类号： H04L12/18 , H04L11/18
摘要： PURPOSE:To attain multiple address communication between terminal devices having different protocols by providing a multiple address communication control section, a multiple address communication control memory and a protocol control section to a relay exchange connected to data terminal devices having different forms of protocol. CONSTITUTION:Data terminal devices 11-1m are connected to a relay line exchange 31 via subscriber exchanges 21-2m by using a different protocol. The relay line exchange 31 consists of a channel device 41, a central processor 42 and a multiple address communication controller. For example, in applying multiple address communication from the data terminal device 11 to the terminal devices 12-1m, data is stored once in a memory in a multiple address communication is applied to the stored data at each terminal device having an identical protocol through the subscriber exchanges 21-2m via the channel device 41 in a form corresponding to each protocol through the control of a central processing unit 42. Thus, multiple address communication is executed easily while including the transmission between terminal devices with different protocols.

20. 发明专利

JPS5569859A TEST CIRCUIT FOR INPUTTOUTPUT EQUIPMENT 失效
公开(公告)号：JPS5569859A
公开(公告)日：1980-05-26
申请号：JP14442378
申请日：1978-11-22
申请人： NIPPON ELECTRIC CO
发明人： INUI YOSHIO , IGAWA IKUTOSHI
IPC分类号： G06F11/22
摘要： PURPOSE:To obtain a simple and small-hardware input-output equipment test circuit which is excellent in economy, reliability and maintenance, by sharing the same counter circuit for any test data pattern generating control and quantity control for test data patterns. CONSTITUTION:An input-output-equipment test circuit consists of counter circuit (CNT) 201 generating timing needed for test operation, test control circuit (CTL) and input-output buffer circuit (BF) 203. Counter circuit 201 functions perfectly as a conventionally-provided test data generating circuit and test control circuit 202 controls only counter circuit 201 and input-output buffer circuit 203, so that the constitution can be simplified. Further, a test data generating circuit is omitted to reduce the hardware, and consequently economy, reliability and maintenance can all be improved.

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