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11. 发明专利

JPS55121547A DATA PROCESSING SYSTEM 失效
公开(公告)号：JPS55121547A
公开(公告)日：1980-09-18
申请号：JP2873179
申请日：1979-03-14
申请人： HITACHI LTD
发明人： KIDA MASAHIKO
IPC分类号： G06F9/22
摘要： PURPOSE:To reduce the number of steps by eliminating the need for a decision on the kind of processing, by assigning a random address from a side which requests a trap and then by executing a microprogram of a trap level. CONSTITUTION:When trap request signal 12 is generated by one or all of controllers 2, 3 and 4, the priority is determined by priority circuit 11 and trap reception signal 13 is sent back to a controller with the highest priority. The controller where signal 13 is sent back sends the initial address of a microprogram of a trap held previously in register 15 onto initial-address transfer path 14. Unit 1 sets the content of transfer line 14 to address register 6, whose content is regarded as the initial address to generate the trap of the microprogram.

12. 发明专利

JPS54116154A MICROPROGRAM CONTROL UNIT 失效
公开(公告)号：JPS54116154A
公开(公告)日：1979-09-10
申请号：JP2207378
申请日：1978-03-01
申请人： HITACHI LTD
发明人： KIDA MASAHIKO
IPC分类号： G06F15/16 , G06F15/173 , G06F15/177
摘要： PURPOSE:To enable to use CS with a plurality sets of CPU for sharing, by constituting the unit with a plurality of CPU's, control storage CS, a plurality of address registers AR, and address pointer AP. CONSTITUTION:CPU's 3 of #1 to #4 and AR1 of CS2 are prepared. Further, by using AR1 of CPU indicated with the pointer register RR5 being the ring counter, the readout of CS2 is made. The data readout is set to the data register DR4 of CPU indicated with PR5. The microprogram muPG set to DR4 is executed with CPU and the address of muPG to be executed is delivered and set to one of AR1 indicated with PR5. After that, PR5 is shifted by one bit, starting the access cycle to the next CPU. Thus, a plurality of CPU's can use the memory of large capacity without waste.

13. 发明专利

JPS527642A INFORMATION PROCESSING EQUIPMENT 失效
公开(公告)号：JPS527642A
公开(公告)日：1977-01-20
申请号：JP8386075
申请日：1975-07-08
申请人： HITACHI LTD
发明人： KIDA MASAHIKO
IPC分类号： G06F9/22
摘要： PURPOSE:To deleate control memory of unnecessary part due to each microinstruction word type and to increase utilization efficiency of control memory.

18. 发明专利

JPS57101450A LOOP TRANSMISSION SYSTEM 失效
公开(公告)号：JPS57101450A
公开(公告)日：1982-06-24
申请号：JP17729180
申请日：1980-12-17
申请人： HITACHI LTD
发明人： KIDA MASAHIKO , HASHIMOTO TOYOKAZU , MATSUMURA HISASHI , WADA HIROYUKI
IPC分类号： H04L12/42
摘要： PURPOSE:To enable response confirmation of a transmission frame while the frame circulates a loop, by providing a loop answer field in the transmission frame of a loop transmission system. CONSTITUTION:In a station of a loop transmission system, a flag pattern is formed at a flag forming circuit 11 and a shifter 6 is transmitted with a station address from a transmission buffer 14 and other data. At the same time, an LA pattern is applied to a shifter 6 from a loop answer field (LA) forming circuit 12. The shifter 6 transmits the frames to a loop transmission line 1. The frames from the transmission line 1 are inputted to a reception shifter 5 and when the LA pattern is received, it is replaced with the output of an LA forming circuit 7 and checked at an error check circuit 17. Thus, the response confirmation of transmission frames can be made while the frame circulates the loop.

19. 发明专利

JPS569823A CHANNEL UNIT 失效
公开(公告)号：JPS569823A
公开(公告)日：1981-01-31
申请号：JP8397379
申请日：1979-07-04
申请人： HITACHI LTD
发明人： KIDA MASAHIKO , KINOSHITA OSAMU
IPC分类号： G06F11/30 , G06F3/00 , G06F13/00
摘要： PURPOSE:To lighten a load on software by processing an abnormal state as a hardware error rapidly by enabling a time supervision from the start of input-output instruction to the end. CONSTITUTION:To perform time control processing, whether timer register updata indication 14 from timer 12 is ON is tested and when so, each sub-channel is scanned to test whether queuing state assignment register 11 has a bit that is ON. For example, when a certain subchannel has device-end queuing assignment bit 16 set to ON, its timer register 13 is updated. Next, whether overflow 15 of timer register 13 is ON is tested and when ON, the result is reported as a hardware error to a host processor to clear timer register 13 and assignment bit 16. When overflow 15 is OFF, the control is transferred to the processing of the next subchannel directly. The above-mentioned processing is performed for all sub-channels.

20. 发明专利

JPS55121566A INFORMATION PROCESSOR 失效
公开(公告)号：JPS55121566A
公开(公告)日：1980-09-18
申请号：JP2773479
申请日：1979-03-12
申请人： HITACHI LTD
发明人： KIDA MASAHIKO , KINOSHITA OSAMU
IPC分类号： G06F15/16 , G06F11/28 , G06F15/177
摘要： PURPOSE:To simplify the investigation of cause when linkage operation among processors is debugged and a fault occurs, by making it possible to stop other random subprocessors at the same time under the stop condition of a random processor. CONSTITUTION:Subprocessors 1, 2 and 3 operate independently one another at a usual time. Subprocessors 1, 2 and 3, having stop control registers 4, 5 and 6 respectively, are mutually connected by stop signal transfer means 10. Further, respective processors are provided with stop control registers and stop signal generators 7, 8 and 9 which generate a stop condition signal under the condition given by the above-mentioned stop signal transfer means. Now, when subprocessor 1 is to stop, the stop signal of subprocessor 1 is transferred to subprocessors 2 and 3 via stop signal transfer means 10, so that subprocessors 2 and 3 will stop simultaneously with subprocessor 1.

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