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11. 发明专利

JPS6153770A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS6153770A
公开(公告)日：1986-03-17
申请号：JP17496484
申请日：1984-08-24
申请人： Hitachi Ltd
发明人： HAIJIMA MIKIO
IPC分类号： H01L21/331 , H01L21/8224 , H01L27/082 , H01L29/06 , H01L29/10 , H01L29/73
CPC分类号： H01L29/0619 , H01L29/0638 , H01L29/1008
摘要： PURPOSE:To realize a very fine structure with a reduced thickness of the surface insulation oxide film and a reduced distance between diffusion layers, by providing the field of a bipolar transistor with a guard ring in which the concentration of a conductive impurity is selectively increased. CONSTITUTION:A guard ring 61 acts to obstruct the formation of a channel inversion layer in the field section between a p type isolating diffusion layer 7 and a p type collector diffusion layer 81. Accordingly, even if the thickness of a surface insulation oxide film 41 is reduced for the purpose of providing a fine structure, the film is prevented from being effected adversely by parasitic MOSFET. Further, since the ring 61 is interposed between the diffusion layers 7 and 81, the effective current amplification factor of a pnp bipolar transistor TR constituted by the diffusion layer 7, an n type epitaxial layer 2 and the diffusion layer 81 is decreased. In this manner, the distance between the diffusion layer 7 and the diffusion layer 81 can be decreased for the purpose of realizing a fine structure without suffering from adverse effect by a parasitic bipolar TR.
摘要翻译：目的：为了实现具有减小的表面绝缘氧化膜厚度和扩散层之间距离减小的非常精细的结构，通过为双极晶体管的场提供选择性增加导电杂质浓度的保护环。构成：保护环61用于阻碍在ap型隔离扩散层7和ap型集电极扩散层81之间的场区中形成沟道反转层。因此，即使表面绝缘氧化物膜41的厚度减小为了提供精细的结构，防止膜被寄生MOSFET不利地影响。此外，由于环61插入在扩散层7和81之间，所以由扩散层7，n +型外延层2和扩散层81构成的pnp双极晶体管TR的有效电流放大系数减小。以这种方式，为了实现精细结构而不会受到寄生双极性TR的不利影响，扩散层7和扩散层81之间的距离可以减小。

12. 发明专利

JPS6057658A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6057658A
公开(公告)日：1985-04-03
申请号：JP16497183
申请日：1983-09-09
申请人： HITACHI LTD
发明人： HAIJIMA MIKIO
IPC分类号： H01L21/822 , H01L21/8222 , H01L27/04 , H01L27/06
摘要： PURPOSE:To obtain MOS capacitance, which is large per an occupied area, by forming irregularities to the surface of a semiconductor substrate and attaching an electrode through an insulating film. CONSTITUTION:An n layer 8 is buried to the (110) face of a p type Si substrate 1 and an n epitaxial layer 2 is superposed, a CVDSiO2 film 10 is superposed on a surface oxide film 9, windows are bored, and grooves 11 having steep slopes are formed by KOH. An SiO2 film 12 and a resist mask 14a are formed and B ions are implanted, the SiO2 films 9, 12, 10 and the resist 14a removed, and a p isolation layer 13 and an SiO2 film 9a are shaped through heat treatment. the grooves 11 may be formed orthogonally. B ions are implanted and diffused through a resist mask to form a p layer 15, and a novel resist mask 16 is executed and As ions are implanted and diffused to shape an n layer 17. When windows are bored to the SiO2 film 9a and an Al electrode 18 is attached, electrodes A, B function as opposite electrodes having MOS capacitance, and an electrode C is connected to low potential and the potential of a p layer is stabilized. According to the constitution, large MOS capacitance is obtained regardless of a small occupied area.

13. 发明专利

JPS59139681A Schottky barrier diode 失效
标题翻译：肖特基二极管二极管
公开(公告)号：JPS59139681A
公开(公告)日：1984-08-10
申请号：JP1271783
申请日：1983-01-31
申请人： Hitachi Ltd
发明人： HAIJIMA MIKIO
IPC分类号： H01L29/47 , H01L29/872 , H01L29/91
CPC分类号： H01L29/872
摘要： PURPOSE:To reduce the formation of alloy pits at a corner and to contrive the stabilization of a Schottky barrier diode to withstand voltage by a method wherein the figure of the main surface of a Schottky barrier part is formed into a polygon or a circular form surrounded with an obtuse angle. CONSTITUTION:A Schottky barrier diode utilizing the rectifying action of a Schottky barrier, which is created at the contact part between a semiconductor and a metal, is the one whereon a Schottky battier was formed by making a metal 4 such as Al, etc., alloy into one part of the surface of an n type Si layer 3 which was epitaxially grown on a p type Si substrate 1 through the intermediary of an N type buried layer 2. At an Al-Si alloy part 7 to make this Schottky barrier, the acuter the angle of a corner is, the more alloy pits are easy to concentrate at the circumference part of the barrier region, but the corner is obtusely formed (90 deg. 135 deg.) by forming the pattern of the Schottky barrier part into an octagon, the formation of alloy pits at the corner part is equalized, current concentration is prevented, the Vf of the Schottky barrier diode is stabilized and leak current is reduced. Besides, this pattern for the barrier is not always limited to one in an octagon. Patterns in an hexagon and other polygons having a large number of angles or ones in a circular form and a rectangle can be used.
摘要翻译：目的：为了减少拐角处的合金凹坑的形成，并且通过以下方法来设计肖特基势垒二极管的稳定性，其中将肖特基势垒部分的主表面的形状形成为多边形或围绕圆形的方法具有钝角。构成：利用在半导体和金属之间的接触部分处产生的肖特基势垒的整流作用的肖特基势垒二极管是通过制造诸如Al等的金属4形成肖特基阻挡层的肖特基势垒二极管，合金成为n型Si层3的表面的一部分，其通过N +型掩埋层2的介质在外延生长在ap型Si衬底1上。在Al-Si合金部分7至使这个肖特基势垒的角度是角的角度，更多的合金凹坑容易集中在阻挡区域的圆周部分，但是通过形成图案的形状（90度135度），角部被钝化地形成将肖特基势垒部分变成八边形，在拐角部分形成合金凹坑相等，防止了电流集中，使肖特基势垒二极管的Vf稳定，漏电流减小。此外，屏障的这种模式并不总是局限在一个八边形。可以使用具有大量角度的六边形和其他多边形中的图案或圆形和矩形的图案。

14. 发明专利

JPS5833880A SEMICONDUCTOR PHOTODETECTOR 失效
公开(公告)号：JPS5833880A
公开(公告)日：1983-02-28
申请号：JP13152881
申请日：1981-08-24
申请人： HITACHI LTD
发明人： HAIJIMA MIKIO , MATSUURA AKIRA
IPC分类号： H01L31/10 , H01L31/11
摘要： PURPOSE:To enhance a photodetector by forming the shallow second conductive type impurity introduce layer on a region isolated from one main surface in the first conductive type semiconductor substrate and using the substrate semiconductor and two P-N junction surfaces with upper and lower surfaces of the layer as a photodetecting region. CONSTITUTION:An N type epitaxial Si layer 1 is formed on a P type substrate 3, is surrounded by a P type isolation layer 4 and is electrically isolated from other element region. A P type layer 5 is formed by B ion implantation in a region isolated from the surface of the layer 1 in such a manner that impurity ion flying distance is deepened by increasing ion implantation energy, for example, up to appox. 200keV, and upper and lower P-N junctions (Xj1, Yj2) are by one ion implantation formed between the layer and an N type Si layer, a light incident from the surface of the element excites electrons-holes at the upper and lower P-N junction surfaces, thereby increasing the sensitivity and the area efficiency and improving the efficiency as a photodetector.

15. 发明专利

JPS5788756A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5788756A
公开(公告)日：1982-06-02
申请号：JP16329480
申请日：1980-11-21
申请人： HITACHI LTD
发明人： HAIJIMA MIKIO
IPC分类号： H01L27/04 , H01L21/822 , H01L27/08 , H01L29/93
摘要： PURPOSE:To obtain a capacity element having little dependency on voltage by providing an N layer divided into a plurality within a P type Si region. CONSTITUTION:An N epitaxial layer on a P type Si substrate 1 is separated by a P layer 3, a P layer 4 is provided and N layers 5-7 are made in the layer 4. An electrode 8 is attached to the central layer 5 and positive voltage is applied thereto to place the layers 6 and 7 surrounding the layer 5 concentrically in a floating state. Since the distance between the respective layers is small, a depletion layer reaches them with ease. When negative voltage is given by an electrode attached to the P layer 4, the depletion layer expands between the layers 5 and 4 and the junction capacity is reduced with the increase in voltage. When the voltage is increased further, the depletion layer reaches the layer 6, the layers 5-6 are made to have the same potential, thus the depletion layer having a large area is formed, and the junction capacity is sharply increased. This action is repeated likewise also for the layer 7, whereby the capacity is changed in an indented form. By selecting the shape, arrangement and difference in density from the layer 4 of the layers 5-7, the element wherein the change in capacity is little dependent on voltage can be obtained.

16. 发明专利

JPS5771161A Semiconductor junction capacity device 失效
标题翻译：半导体连接能力设备
公开(公告)号：JPS5771161A
公开(公告)日：1982-05-01
申请号：JP14696180
申请日：1980-10-22
申请人： Hitachi Ltd
发明人： HAIJIMA MIKIO
IPC分类号： H01L27/04 , H01L21/822 , H01L27/08
CPC分类号： H01L27/0805
摘要： PURPOSE:To provide the high capacitor with a small area for high intengration by a method wherein the first conductivity-type layer is provided at an epitaxial layer on the first conductivity-type substrate provided with the second conductivity- type buried layer by an isolation diffusion process and the second conductivity-type layer is formed in this region. CONSTITUTION:For example, an n buried layer 3 is diffused on a p-substrate and after applying epitaxial growth to an n layer 4, p layers 6, 7 are formed on an isolation region and the buried layer 3 by an isolation diffusion process. Next, a p layer 8 superimposing a part of the p layer 8 is provided on the layer 7 by a base process, then after diffusion an n regions 7, 8 by an emitter process, Al contact electrodes A, B are formed in the regions 8 and 9. In this way, capacitor device (about twice conventional capacitance value) consisting of unction capacitor c1, between the layer 7 and the buried layer 3, capacitor c2 between the layers 7, 8 and the n layer 9, capacitor c3 between the layers 7, 8 and the n epitaxial layer, and ground capacitor c4 between the buried layer 3 and the n substrate 1 can be manufactured on the same area.
摘要翻译：目的：通过一种方法提供具有小面积的高电容器的高电容器，其中第一导电类型层通过隔离扩散装置设置在设置有第二导电型掩埋层的第一导电类型基板上的外延层处在该区域形成第二导电型层。构成：例如，n +掩埋层3扩散到p衬底上，并且在将外延生长施加到n +层4之后，在隔离区上形成p + 6层7，并且埋层3通过隔离扩散过程。接下来，通过基底工艺在层7上设置叠加p +层8的一部分的p +层8，然后在扩散之后，将n +层<9> 在区域8和9中形成有由接触电极A，B构成的p +区域7,8。这样，在层7和7之间由电容器c1构成的电容器器件（约为常规电容值的两倍）掩埋层3，层7,8和n +层9之间的电容器c2，层7,8和n +外延层之间的电容器c3以及掩埋层3和可以在同一区域上制造n基板1。

17. 发明专利

JPS52113183A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS52113183A
公开(公告)日：1977-09-22
申请号：JP2924376
申请日：1976-03-19
申请人： HITACHI LTD
发明人： HAIJIMA MIKIO , HORIE NOBORU
IPC分类号： H01L27/04 , H01L21/822
摘要： PURPOSE:To obtain a semiconductor device having a higher electrostatic breakdown strength by constructing all the resistances connected to external terminals from internal resistances inside the epitaxial layer which is electrically separated.

18. 发明专利

JPH04741A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND LAYOUT SYSTEM THEREOF 失效
公开(公告)号：JPH04741A
公开(公告)日：1992-01-06
申请号：JP10030390
申请日：1990-04-18
申请人： HITACHI LTD
发明人： HINO TETSURO , NISHIKATA ASAO , KONDO SHIZUO , HAIJIMA MIKIO , SHIRAISHI YOICHI
IPC分类号： H01L21/82
摘要： PURPOSE:To increase element density by connecting a wiring for connecting blocks arranged in hierarchy on a side of a block as directly as possible. CONSTITUTION:A block is arranged without providing a wiring region among blocks. Wiring among blocks is connected on a side of adjacent blocks which are in contact with each other. When blocks are apart, they are connected by a wiring of a minimum distance to cross with a longitudinal direction of a channel among blocks. When another block exists between blocks to be connected, a passing wiring is formed in the block between blocks and a plurality of dummy terminals connected thereto are provided. A terminal of each block is connected to each dummy terminal on a side. As for layout of an interior of a block, an element is arranged to shorten a distance to an external terminal of a block.

19. 发明专利

JPH02250369A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02250369A
公开(公告)日：1990-10-08
申请号：JP7065489
申请日：1989-03-24
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： KANAZAWA TAKAMITSU , HAIJIMA MIKIO
IPC分类号： H01L21/822 , H01L21/8222 , H01L27/04 , H01L27/06
摘要： PURPOSE:To maintain a device close to thermal equilibrium by a method wherein one or more of a plurality of semiconductor elements are divided into a plurality of pieces to have the other element interposed or so that they are mutually interposed. CONSTITUTION:One or more of a plurality of semiconductor elements 2 are divided into a plurality of pieces to have the other element interposed or so that they are mutually interposed. For example, as shown in the figure, a transistor q2 which is especially large in emitter size is divided into two transistors q2A, q2B to be arranged so that the other transistor q1 is interposed between them. Thus even if the temperature of q2A is lower than that of q1 as reference, the temperature of entire q2 is averaged, so that q1 and q2 can have characteristics equal or approximate to those in thermal equilibrium.

20. 发明专利

JPS62105525A SEMICONDUCTOR INTEGRATOR CIRCUIT DEVICE 失效
公开(公告)号：JPS62105525A
公开(公告)日：1987-05-16
申请号：JP24397285
申请日：1985-11-01
申请人： HITACHI LTD
发明人： HAIJIMA MIKIO , INABA TORU
IPC分类号： H03K19/0175 , H01L21/8249 , H01L27/06 , H03K19/00
摘要： PURPOSE:To prevent the gate insulating film of a MOS transistor TR from being polarized and to stabilize the operation of a semiconductor integrated circuit device by providing a diode which clamps the gate input voltage of the CMOS TR of the input circuit of a digital circuit part to the current voltage side on the side of the digital circuit part. CONSTITUTION:An analog/digital mixed type semiconductor integrated circuit device is provided with the digital circuit 1 as the 1st circuit part and an input circuit part 1a composed of a CMOS TR, and the 1st circuit part is operated at a specific voltage of 5V as an operating source voltage Vdd-Vss. Further, a linear circuit part 2 as the 2nd circuit part and an output circuit part 2a on the side of the circuit 2 are provided and this 2nd circuit part is operated at a specific voltage of 12V as an operating voltage Vcc higher than the voltage Vdd-Vcc. The diode D1 for gate input voltage clamping is connected between the connection point between the output circuit part 2a of the 2nd circuit part and the input circuit part 1a of the 1st circuit part and the voltage Vdd. Then input voltages to TRs M1 and M2 of the input circuit part 1a are clamped to prevent the gate insulating film from being polarized.

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