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11. 发明专利

JP2000011014A DEVICE AND METHOD FOR GENERATING JUMPER WIRING FIGURE 失效
公开(公告)号：JP2000011014A
公开(公告)日：2000-01-14
申请号：JP17558098
申请日：1998-06-23
申请人： HITACHI LTD
发明人： NODA TAKAAKI , AONO MASAHIRO , KASHIWAGI MIHOKO , SOEJIMA YUICHI , MURAYAMA YUKIJI , TSUKADA SHIGEKI , SAITO KEIICHI
IPC分类号： H05K3/00 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To prevent wiring for a noise countermeasure again after executing jumper wiring by means of performing the countermeasure taking into consideration an electric noise of which a jumper wire receives by comparing an allowable wiring length corresponding to the signal of a route with the whole length of the route, judging it and designating a jumper wiring material in accordance with the judgement result. SOLUTION: The total sum of jumper wiring route segment lengths is calculated (S14). When the value exceeds an allowable wiring length which requires a noise countermeasure (S15) and also the noise countermeasure is not executed yet (S16), the search of FROM and TO points at a ground side is performed (S17) in order to execute noise countermeasure processing, for example, a twist pair-wiring with the ground. The search finds a pin or a buyer connected to the nearest ground making the signal side FROM points (or signal side TO points) as a base point. As the result, the ground side FROM and TO points against the signal side FROM and TO points are searched (S18). The wiring is ended since the whole jumper wiring routes are established (S19).

12. 发明专利

JP2561636B2 失效
公开(公告)号：JP2561636B2
公开(公告)日：1996-12-11
申请号：JP16637284
申请日：1984-08-10
申请人： HITACHI LTD
发明人： NODA TAKAAKI , KOKUBO MASARU
IPC分类号： H03K7/08 , H02M7/48 , H03K5/01 , H03K5/04

13. 发明专利

JPH07264247A PULSE TRANSMISSION CIRCUIT 失效
公开(公告)号：JPH07264247A
公开(公告)日：1995-10-13
申请号：JP7532194
申请日：1994-03-22
申请人： HITACHI LTD
发明人： NODA TAKAAKI
IPC分类号： H03K19/003 , H04L25/02
摘要： PURPOSE:To prevent deterioration in the performance and reliability by selecting a level of an output signal for an S/T interface LSI or the like including the pulse transmission circuit within the standard level CONSTITUTION:In an LSI mounted with the pulse transmission circuit PT including operational amplifiers acting as a voltage follower via a source follower circuit and a current limit MOSFET receiving a gate voltage GP1 at its gate and including a reference current generating circuit MCG forming a prescribed gate voltage and an internal power supply buffer VBB transmitting an internal voltage VB1 for setting a level of an output signal to a drive circuit PD as an internal voltage VC, a gate voltage buffer GPB is provided between an output terminal of the reference current generating circuit MCG and a gate of the current limit MOSFET and a feedback circuit comprising a CMOS inverter with a comparatively high threshold level and a prescribed capacitance means inverting and differentiating a change in the drain potential of the current limit MOSFET and giving the resulting change to the gate is provided between a drain and a gate of the current limit MOSFET.

14. 发明专利

JPH06216772A A/D CONVERTER AND COMPLETELY DIFFERENTIAL OPERATIONAL AMPLIFIER CIRCUIT 失效
公开(公告)号：JPH06216772A
公开(公告)日：1994-08-05
申请号：JP2177793
申请日：1993-01-14
申请人： HITACHI LTD
发明人： NODA TAKAAKI
IPC分类号： H03F3/45 , H03M1/08 , H03M1/12
摘要： PURPOSE:To provide an A/D converter capable of suppressing the deterioration of S/H characteristic by the influence of a noise to a minimum even when the converter is loaded by mixing with a large scale digital circuit. CONSTITUTION:A differential signal forming circuit 6 as an invertible amplifier is constituted by using a completely differential operational amplifier circuit 4 equipped with an in-phase feedback input terminal CMF and a resistor means. An analog input signal of single end is converted to a differential signal by inputting an analog signal to the negative input terminal side of the completely differential operational amplifier circuit, connecting the positive input terminal side to analog signal ground, and feeding back the midpoint potential of differential output to the in-phase feedback input terminal. After the differential signal is A/D-converted, a digital signal is converted to the digital signal of single end by applying digital substraction to it.

15. 发明专利

JPH02245810A REFERENCE VOLTAGE GENERATING CIRCUIT 失效
公开(公告)号：JPH02245810A
公开(公告)日：1990-10-01
申请号：JP6612389
申请日：1989-03-20
申请人： HITACHI LTD
发明人： HORIGUCHI SHINJI , ETO JUN , AOKI MASAKAZU , ITO KIYOO , NAKAGOME YOSHINOBU , MIYAKE NORIO , NODA TAKAAKI
IPC分类号： G11C11/407 , G05F3/24 , G11C11/401 , G11C11/409 , H03K19/00
摘要： PURPOSE:To generate a stable voltage with less fluctuation due to an external power source voltage and a temperature by providing a current mirror means holding first and second currents flowing to in first and second FETs to be a constant rate and setting the potential difference of the inter-drain or the inter-source of first and second FETs to be a reference voltage. CONSTITUTION:P channel MOSFETs Q64 and Q65 share a gate and a source, and constitute what is called a current mirror circuit 70. It operates in such a manner that the rate of the drain current I1 of Q64 and the drain current I2 of Q65 becomes constant. The potential difference when the current of the constant rate is made to flow in FETs Q64 and Q65 is taken out and set to be the reference voltage. Since two FETs Q64 and Q65 different in a threshold voltage are used in an enhancement type, the difference of the threshold voltage can be set to be considerably small. Thus, the matching of the characteristics of two FETs is facilitated and the stable reference voltage can be obtained.

16. 发明专利

JPS62249212A REFERENCE VOLTAGE GENERATION CIRCUIT 失效
公开(公告)号：JPS62249212A
公开(公告)日：1987-10-30
申请号：JP9204486
申请日：1986-04-23
申请人： HITACHI LTD
发明人： NODA TAKAAKI
IPC分类号： G05F3/24
摘要： PURPOSE:To obtain a voltage generation circuit having no oscillation, by performing a control to turn on a MOSFET having a low threshold voltage compulsorily, and to detect the voltage of the MOSFET having a high threshold voltage. CONSTITUTION:A start-up circuit 1 detects the voltage generated at a MOSFETQ6 whose threshold value is set higher than that of a MOSFETQ5, at a detection circuit 2, and operates the MOSFETs Q5 and Q6 to be turned on compulsorily at a power supply applying time based on the above result. In a constant current circuit 3, a current mirror circuit consisting of P- MOSFETs Q7 and Q8 is provided at a power source terminal Vdd side, and also, a ratio type CMOS inverter circuit consisting of a P-MOSFETQ9 and an N-MOSFETQ10 are coupled to limit a current flow on the MOSFETQ8 smaller, and it is constituted so that a current equivalent to the one permitting to flow on the MOSFETQ8 is permitted to flow on the MOSFETQ7.

17. 发明专利

JP2001251032A PRINTED WIRING BOARD, PRINTED WIRING BOARD DESIGN SUPPORTING DEVICE AND SYSTEM OF MANUFACTURING PRINTED WIRING BOARD 失效
公开(公告)号：JP2001251032A
公开(公告)日：2001-09-14
申请号：JP2000057793
申请日：2000-03-02
申请人： HITACHI LTD
发明人： SOEJIMA YUICHI , NODA TAKAAKI , KAWAI SHINICHIRO , ISONO MASAHIRO
IPC分类号： H05K1/02 , G06F17/50 , H05K3/00
摘要： PROBLEM TO BE SOLVED: To provide a printed wiring board in which an outline of a signal to be probed can be recognized without referring to specifications or the like at the time of operation check or an inspection. SOLUTION: For at least one of the factors constituting a wiring pattern formed on a printed wiring board, an indicator showing the characteristics of a signal flowing through the wiring factor is visualized on the surface of the printed wiring board. For example, wiring information 7, signal type information 8, frequency information 9, signal operation level information 10, input/ output pin information 11 and bidirectional information 12 are shown on the surface of the wiring board. Also, pin number information 13 for silk-screen printing the pin number of a pin connecting to a signal line and signal name information 14 for silk-screen printing the signal name are shown near a via 6 of the signal line and the repair pad 5 thereof.

18. 发明专利

JPH07211781A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH07211781A
公开(公告)日：1995-08-11
申请号：JP661994
申请日：1994-01-25
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： SAGARA SHUSAKU , NODA TAKAAKI
IPC分类号： H01L21/8234 , H01L27/088
摘要： PURPOSE:To provide an excellent semiconductor integrated circuit device with reduced difference in characteristics between a pair of MOSFETs, and a method whereby such a semiconductor integrated circuit device is simply obtained. CONSTITUTION:Each of a pair of a first and a second MOSFETs is divided into a plurality of MOSFETs. The characteristics of the resultant MOSFETs can be unified by connecting in series either or both of the group of all the source electrodes 28-32 and the group of all the drain electrodes 33-36 of the resultant MOSFETs through a common electrode wiring layer 38. This makes similar the characteristics of the first and second MOSFETs, which obtains an excellent semiconductor integrated circuit device with reduced difference in characteristics between them.

19. 发明专利

JPH0685562A COMPARATOR WITH OFFSET CANCEL CIRCUIT 失效
公开(公告)号：JPH0685562A
公开(公告)日：1994-03-25
申请号：JP23820592
申请日：1992-09-07
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： MOROKUNI SHINICHI , SAKAGUCHI JIRO , SATOU TEN , NODA TAKAAKI , KASAI ATSUSHI , MASUMURA ATSUO , SHIMAUCHI HIROAKI
IPC分类号： H03K5/08 , H03F3/34 , H03M1/10
摘要： PURPOSE:To provide the high-speed and high-accuracy voltage comparator which cancel offset without decelerating the operating speed by connecting a switch for equalize between the output terminals of differential amplifier circuits in a first step and temporarily turning on the switch for equalizer at the time of starting the charge of an offset potential to a coupling capacitor. CONSTITUTION:Between the input terminal of a differential amplifier circuit 12 in the next step and a ground point, switches S5 and S6 are connected for charging/discharging coupling capacitors C1 and C2 and constitute an offset charging circuit 13 together with the C1 and C2. Since the coupling capacitors C1 and C2 are charged with potential difference close to the offset potential of a differential amplifier circuit 11 in the first step, time to charge the offset potential to the coupling capacitors C1 and C2 by turning on the switches S5 and S6 is shortened, timing for a control signal phic to rise to a high level is fastened, and the amplifying operation of the differential amplifier circuit 12 in the next step can be accelerated.

20. 发明专利

JPH02244488A LARGE SCALE INTEGRATED CIRCUIT 失效
公开(公告)号：JPH02244488A
公开(公告)日：1990-09-28
申请号：JP6376489
申请日：1989-03-17
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HORIGUCHI SHINJI , AOKI MASAKAZU , ITO KIYOO , NAKAGOME YOSHINOBU , IKENAGA SHINICHI , ETO JUN , MIYAKE NORIO , NODA TAKAAKI , TANAKA HITOSHI
IPC分类号： G11C11/413 , G05F3/24 , G11C11/401 , G11C11/407 , G11C11/409 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
摘要： PURPOSE:To stabilize the operation by using two pieces of FETs of an enhancement type whose threshold voltages are different, fetching a voltage difference at the time when a current of a prescribed ratio is allowed to flow to them and setting it as a reference voltage. CONSTITUTION:This circuit consists of N channel MOSFETs Q61-Q63 and P channel MOSFETs Q64, Q65, and a positive voltage is applied from an external power source Vcc. In this case, the N channel MOSFETs Q61-Q63 consist of enhancement type FETs Q62, Q63 having a standard threshold voltage VTE and an enhancement type FET Q61 having a threshold voltage VTEE being higher than VTE. In such a way, since two pieces of FETs of an enhancement type whose threshold voltages are different are used, a difference of those threshold voltages can be made small enough. Accordingly, characteristics of two pieces of FETs can be fitted easily, and a stable reference voltage can be obtained. In such a way, the operation is stabilized.

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