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11. 发明专利

JP2001016092A SEMICONDUCTOR LOGIC CIRCUIT 失效
公开(公告)号：JP2001016092A
公开(公告)日：2001-01-19
申请号：JP18473899
申请日：1999-06-30
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： KANETANI KAZUO , NANBU HIROAKI , YAMAZAKI SU , KUSUNOKI TAKESHI , ARAKAWA FUMIHIKO
IPC分类号： H03K19/096
摘要： PROBLEM TO BE SOLVED: To shorten the delay time of a logic circuit by installing an input or reference transistor closer to a power source, as compared to a decision transistor and installing decision transistors which independently activate complementary output nodes. SOLUTION: An input transistor MN1 of a second logic circuit 2 and a reference transistor MNB of a third logic circuit 3 are installed on a side closer to a power source VSS compared to a decision transistor MNL (first logic circuit 1) and a decision transistor MNR. J decision transistors are divided into the decision transistors MNL and MNR, and complementary output nodes (Q and IQ) are activated independently. A control signal ϕ1 is inputted to the gate of the decision transistor MNL, and a control signal ϕ2 is inputted to the gate of the decision transistor MNR. The control signal ϕ1 is inputted to the gate of a pull-up transistor MPL, and the control signal ϕ2 is inputted to the gate of the pull-up transistor MPR.

12. 发明专利

JP2001016090A SEMICONDUCTOR CIRCUIT 失效
公开(公告)号：JP2001016090A
公开(公告)日：2001-01-19
申请号：JP18290199
申请日：1999-06-29
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NANBU HIROAKI , KANETANI KAZUO , YAMAZAKI SU , ARAKAWA FUMIHIKO , KUSUNOKI TAKESHI
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/786 , H03K19/094
摘要： PROBLEM TO BE SOLVED: To eliminate changes in operation speed by connecting the body of a field effect transistor with first, second or third power sources through a specified resistor. SOLUTION: In a semiconductor circuit comprising a field effect transistor MN1 (MP1) installed between a first power VSS (VDD) and a second power VDD (VSS), a body BMN1 (BMP1) of a field effect transistor MN1 (MP1) and a third power VBMN1 (VBMP1) are connected via a resistor RBMN1 (RBMP1). When a capacitance between the gate of the field effect transistor MN1 (MP1) and the body BMN1 (BMP1) is defined as C1, the switching time of a voltage signal inputted to the gate of the field effect transistor MN1 (MP1) as τ and the operation cycle time of a semiconductor circuit as T, a resistance value R of the resistor RBMN1 (RBMP1) satisfies the inequality 1e-2×τ

13. 发明专利

JP2001014855A SEMICONDUCTOR CIRCUIT 失效
公开(公告)号：JP2001014855A
公开(公告)日：2001-01-19
申请号：JP18473799
申请日：1999-06-30
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： YAMAZAKI SU , NANBU HIROAKI , KANETANI KAZUO , KUSUNOKI TAKESHI , ARAKAWA FUMIHIKO
IPC分类号： G11C11/41
摘要： PROBLEM TO BE SOLVED: To shorten a recovery time and an operation cycle time while holding load capacity connected to a pre-charge control signal line at a fixed value by providing an equalizing circuit between a pair of complementary signal lines which equalizes potentials of both signal lines being adjacent between complementary signal lines being adjacent to a line other than a pair of complementary signal line pre-charge circuit. SOLUTION: A pair of complementary signal line pre-charge circuits PA1-PA3 equalizes potential of a pair of complementary signal lines SP1/SN1-SP3/SN3 to a power source. Equalizing circuits between a pair of complementary signal lines PB1, PB2 are controlled by a control signal AB, and equalizes potentials of signal lines SN1 and SP2, signal lines SN2 and SP3 being adjacent between a pair of complementary signal lines SP1/NP1-SP3/NP3 synchronizing with the pre-charge circuits PA1-PA3. In order to keep load capacity connected to the control signal line AB and prescribed fixed value, size of the ore-charge circuits PA1-PA3 is made small because of providing the equalizing circuits PB1, PB2.

14. 发明专利

JP2003163584A VARIABLE DELAY CIRCUIT AND SYSTEM LSI USING VARIABLE DELAY CIRCUIT 审中-公开
公开(公告)号：JP2003163584A
公开(公告)日：2003-06-06
申请号：JP2001358739
申请日：2001-11-26
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： YAMAZAKI SU , NANBU HIROAKI , KANETANI KAZUO , ARAKAWA FUMIHIKO , KUSUNOKI TAKESHI
IPC分类号： G11C11/407 , G06F1/06 , G06F15/78 , G11C11/4076 , H03K5/04 , H03K5/13
摘要： PROBLEM TO BE SOLVED: To provide a system LSI of high-speed, small area and low power consumption by reducing the number of offsets, variable notch widths and transistors at a variable delay circuit. SOLUTION: A multiplexer in the variable delay circuit is configured with a NMOS dynamic logic circuit. In order to give a duty ratio adjustment function to a delay generating circuit DGD composed of multiple stage invertors within the variable delay circuit 2, (two) input NAND gates 20 and 30 of which input is an input signal S and delay outputs G1 and G2 of previous stage, are provided. According to this arrangement, the duty ratio is simultaneously decreased in the process of delaying signals. COPYRIGHT: (C)2003,JPO

15. 发明专利

JP2001325318A DESIGNING METHOD FOR DEVICE AND STORAGE MEDIUM STORED WITH PROGRAM BASED UPON THE SAME 失效
公开(公告)号：JP2001325318A
公开(公告)日：2001-11-22
申请号：JP2000148582
申请日：2000-05-16
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NANBU HIROAKI , KANETANI KAZUO , YAMAZAKI SU , ARAKAWA FUMIHIKO , KUSUNOKI TAKESHI
IPC分类号： G06F17/50
摘要： PROBLEM TO BE SOLVED: To accurately find optimum design parameters in a short time when a device which has many design parameters and characteristic values to be considered is designed. SOLUTION: A total characteristic evaluation function E including characteristic values tpd and sa is set, and calculated by finding tpd and sa for a design parameter wg by a characteristic simulator and a characteristic calculating program, and next wg is found from the result according to fixed rules and tpd and sa for this wg are found to E. This operation is repeated.

16. 发明专利

JP2001014856A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JP2001014856A
公开(公告)日：2001-01-19
申请号：JP18474299
申请日：1999-06-30
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： KUSUNOKI TAKESHI , ARAKAWA FUMIHIKO , NANBU HIROAKI , KANETANI KAZUO , YAMAZAKI SU
IPC分类号： G11C11/41
摘要： PROBLEM TO BE SOLVED: To shorten a cycle time without increasing an access time by providing a second pre-charge circuit which operates after detecting finish of write-in and finishes operation after detecting that a potential of a pair of bit line is pre-charged to a high potential. SOLUTION: A semiconductor memory comprising memory cells MC1-MC4, bit line pre-charge circuits PR1, PR2, write-in circuits WR1, WR2 is provided with bit line pre-charge circuits PW1, PW2 for write-in only. In the bit line pre-charge circuit PW1 (PW2) for write-in only, when a write-in control signal WP is low potential and either of bit lines BL1, BR1 is low potential, that is, only for a period from the time of finish of write-in operation to the time at which the bit lines BL1, BR1 are pre-charged to a high potential, PMOS transistors MP3-MP5 are conducted. Thereby, a recovery time after write-in operation can be shortened, and a cycle time can be shortened.

17. 发明专利

JPH11250669A SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM 失效
公开(公告)号：JPH11250669A
公开(公告)日：1999-09-17
申请号：JP4648398
申请日：1998-02-27
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： KUSUNOKI TAKESHI , OHATA KENICHI , ARAKAWA FUMIHIKO , NANBU HIROAKI , KANETANI KAZUO , YAMAZAKI SU , HIGETA KEIICHI , NISHIYAMA MASAHIKO
IPC分类号： G11C11/413
摘要： PROBLEM TO BE SOLVED: To reduce a chip occupying area by a circuit configuration for giving a voltage from a test external terminal to a memory cell at the time of screening by giving an output voltage from an internal power source voltage generator to the cell in a normal operating time state. SOLUTION: An external terminal VEXT directly led from a power source supply line VCM of a memory cell out of a chip is provided. And, an internal power source voltage generator VCMG has a function of an output terminal OUT to a high impedance state. Thus, an insertion of a MOS switch in series between the power source supply line of the cell, the internal power source voltage generator and a testing external terminal is not required. No voltage drop occurs at the switch. And, a chip occupying area of the circuit for giving an operating power to the cell can be reduced.

18. 发明专利

JPH0863244A CURRENT SOURCE CIRCUIT 失效
公开(公告)号：JPH0863244A
公开(公告)日：1996-03-08
申请号：JP20073394
申请日：1994-08-25
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NANBU HIROAKI , KANETANI KAZUO , IDEI YOJI , MASUDA TORU , YAMAZAKI SU , OHATA KENICHI , KUSUNOKI TAKESHI , YAMAGUCHI KUNIHIKO , HIGETA KEIICHI , USAMI MASAMI , ANDO KAZUMASA
IPC分类号： G05F3/22 , H03F3/343
摘要： PURPOSE: To lower the source voltage of the current source circuit which is made small in the temperature dependency and source voltage dependency of a current value. CONSTITUTION: A start-up circuit SU which turns ON when the voltage difference between a source voltage VEE and a ground voltage reaches a specific voltage to supply a current and reaches high impedance when transistors(TR) Q2 and Q3 turn ON as a result and then TRs Q1 and QCS turn ON is connected to the bases of the Q2 and Q3. A current source I1 uses a current which flows when the Q2 turns ON. One end of a resistance RE is connected directly to the VEE and the other end is connected to the ground voltage through a high- impedance circuit (QCS, Q3, and I1) and also connected to the VEE thorugh a low-impedance circuit (QCS, Q3, Q2, R2, and Q1). The ratio of emitter current density of the Q1, Q2, Q3, and QCS is set to 1:1:1/20:1.

19. 发明专利

JP2001016091A SEMICONDUCTOR CIRCUIT 失效
公开(公告)号：JP2001016091A
公开(公告)日：2001-01-19
申请号：JP18473699
申请日：1999-06-30
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： NANBU HIROAKI , KANETANI KAZUO , YAMAZAKI SU , ARAKAWA FUMIHIKO , KUSUNOKI TAKESHI
IPC分类号： H03K19/0948
摘要： PROBLEM TO BE SOLVED: To make compatible reduction of both the switching time at rising of the input of the semiconductor circuit and falling of the input at switching time. SOLUTION: This semiconductor circuit is so controlled that an N-channel field effect transistor (MN2) is set to off, when the output of the semiconductor circuit is at L level and a P-channel field effect transistor (MP2) is set to off, when the output is at H level. A logical threshold voltage can be made low then the input rises and high when the input falls, so that shortenings of the switching time when the input rises and the switching time when the input falls are made compatible.

20. 发明专利

JP2002214309A SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR MEMORY 失效
公开(公告)号：JP2002214309A
公开(公告)日：2002-07-31
申请号：JP2001012607
申请日：2001-01-22
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： KANETANI KAZUO , NANBU HIROAKI , YAMAZAKI SU , ARAKAWA FUMIHIKO , KUSUNOKI TAKESHI , HIGETA KEIICHI
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3185 , G11C29/14 , G11C29/00
摘要： PROBLEM TO BE SOLVED: To allow a zero input current test and a slight light detecting test in the operation of the evaluating operation of a dynamic type semiconductor integrated circuit having a precharge operation and the evaluating operation during one cycle to facilitate a diagnostic test and a failure analysis with higher precision. SOLUTION: The dynamic type semiconductor integrated circuit is formed of a semiconductor integrated circuit having a general operation mode and a test mode. The switching of both the operation modes is performed by an operation mode switching signal, and the pulse width of an activation signal for internal circuit is controlled so as to be constant depending on the magnitude of the operation cycle time in the general operation mode and so as to be extended or shortened following the magnitude of the operation cycle time in the test mode.

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