专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明专利

JP2014013851A Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2014013851A
公开(公告)日：2014-01-23
申请号：JP2012151027
申请日：2012-07-05
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： UCHIYAMA HIROYUKI , WAKANA HIRONORI
IPC分类号： H01L29/786 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To provide a technology of enabling improvement of performance of a semiconductor device.SOLUTION: A thin film transistor 10 includes a wire member 12 supported on a support substrate 11. The wire member 12 has as a core, a conductor wire 20 which functions as a gate line, and a surface of the conductor wire 20 is sequentially covered with a gate insulation film 21 and a channel layer 22. The wire member 12 is supported in a sandwiched manner by source/drain electrodes 13, 14 formed on the support substrate 11. The source/drain electrodes 13, 14 are electrically connected with the channel layer 22 at positions away from each other along a circumferential direction of a cross section of the wire member 12.
摘要翻译：要解决的问题：提供能够提高半导体器件的性能的技术。解决方案：薄膜晶体管10包括支撑在支撑基板11上的线构件12.线构件12具有作为芯的导线 20，其用作栅极线，并且导体线20的表面依次被栅极绝缘膜21和沟道层22覆盖。线构件12以形成的源极/漏极13,14夹持的方式被支撑源极/漏极13,14沿着线构件12的横截面的圆周方向彼此远离的位置与沟道层22电连接。

12. 发明专利

JP2013125782A Oxide semiconductor device 审中-公开
标题翻译：氧化物半导体器件
公开(公告)号：JP2013125782A
公开(公告)日：2013-06-24
申请号：JP2011272337
申请日：2011-12-13
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： UCHIYAMA HIROYUKI , KAWAMURA TETSUSHI , WAKANA HIRONORI , OZAKI HIROAKI , YAMAZOE TAKANORI
IPC分类号： H01L29/786 , G02F1/1368
摘要： PROBLEM TO BE SOLVED: To provide an oxide semiconductor device having good characteristics and high reliability even when a flexible substrate is used.SOLUTION: An oxide semiconductor device has: a gate electrode 2; a gate insulating layer 3 provided on the gate electrode 2; a channel part provided on the gate electrode 2 via the gate insulating layer 3; and source-drain electrodes 6 electrically connected with the channel part. The channel part includes an oxide semiconductor layer 5 and a conductive layer 4. At least one of the source-drain electrodes 6 is connected to the conductive layer 4 via the oxide semiconductor layer 5.
摘要翻译：要解决的问题：即使使用柔性基板，也提供具有良好特性和高可靠性的氧化物半导体器件。解决方案：氧化物半导体器件具有：栅电极2; 设置在栅极电极2上的栅极绝缘层3; 经由栅极绝缘层3设置在栅极电极2上的沟道部分; 以及与沟道部电连接的源极 - 漏极电极6。沟道部分包括氧化物半导体层5和导电层4.至少一个源 - 漏电极6经由氧化物半导体层5连接到导电层4.版权所有（C）2013，JPO和INPIT

13. 发明专利

JP2010192560A Method of manufacturing field effect transistor having oxide semiconductor 有权
标题翻译：制造具有氧化物半导体的场效应晶体管的方法
公开(公告)号：JP2010192560A
公开(公告)日：2010-09-02
申请号：JP2009033577
申请日：2009-02-17
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： WAKANA HIRONORI , UCHIYAMA HIROYUKI , KAWAMURA TETSUSHI , SAITO SHINICHI
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L21/02631 , H01L21/02554 , H01L21/02565 , H01L29/7869
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a field effect transistor which has high alignment accuracy between a gate electrode and source and drain electrodes and achieves a transparent device inexpensively. SOLUTION: Since a patterned light blocking film 102 is formed on the rear side of a substrate 101 and used as a photomask for forming a pattern of the gate electrode 103 and a pattern of the source and drain electrodes 108 on the front side of the substrate, the number of photomasks is reduced, and self-alignment between the gate electrode and the source and drain electrodes is carried out, thereby improving the alignment accuracy of these electrodes. Thereby, the method of manufacturing the high-accuracy inexpensive field effect transistor can be provided. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种在栅电极和源漏电极之间具有高对准精度的场效应晶体管的制造方法，并且廉价地实现透明器件。解决方案：由于在基板101的背面形成有图案遮光膜102，并且用作用于形成栅电极103的图案的光掩模和前侧的源极和漏电极108的图案，光掩模的数量减少，并且进行栅电极与源漏电极之间的自对准，从而提高这些电极的对准精度。由此，可以提供制造高精度廉价的场效应晶体管的方法。版权所有（C）2010，JPO＆INPIT

14. 发明专利

JP2010140919A Oxide semiconductor device, manufacturing method thereof, and active matrix substrate 审中-公开
标题翻译：氧化物半导体器件及其制造方法和有源矩阵衬底
公开(公告)号：JP2010140919A
公开(公告)日：2010-06-24
申请号：JP2008312814
申请日：2008-12-09
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： UCHIYAMA HIROYUKI , KAWAMURA TETSUSHI , WAKANA HIRONORI
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/7869 , H01L21/02554 , H01L21/02565 , H01L21/02617 , H01L21/28291 , H01L27/10873 , H01L27/112 , H01L27/11206 , H01L27/1225 , H01L27/3262 , H01L51/5206
摘要： PROBLEM TO BE SOLVED: To solve the problem that a characteristic which an oxide semiconductor material originally has cannot be utilized due to a difference in work function and difficulty in reducing contact resistance between a metal electrode material and an oxide semiconductor thin-film transistor such as indium oxide gallium zinc and zinc oxide tin. SOLUTION: A phenomenon is utilized in which contact resistance between a semiconductor oxide and metal varies depending on the percentage of added oxygen in gas which is introduced at the film-formation of the semiconductor oxide such as indium oxide gallium zinc and zinc oxide tin. The contact resistance can be suppressed by raising the percentage of added oxygen to 10% or higher, however, in contrast, a threshold potential shift tends to increase. Therefor, a region from the surface where a metal contacts with the semiconductor oxide down to as deep as at least 3 nm is formed as a contact layer with the percentage of added oxygen being 10% or higher while the region being a main channel layer is formed at the percentage of the added oxygen of 10% or lower to form a multilayer structure. Thus, both an ohmic property relative to an electrode metal and reliability in suppressing the threshold potential shift can be made compatible. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题为了解决由于功函数的不同而难以使金属电极材料与氧化物半导体薄膜之间的接触电阻降低的问题，原来具有氧化物半导体材料的特性不能利用的问题晶体管，如氧化铟镓锌和氧化锌锡。解决方案：利用半导体氧化物和金属之间的接触电阻根据在氧化铟镓锌和氧化锌等半导体氧化物成膜时引入的气体中添加的氧气的百分比而变化的现象锡。可以通过将添加的氧的百分比提高到10％以上来抑制接触电阻，然而，相反，阈值电位偏移趋于增加。因此，形成从金属与半导体氧化物接触至深度至少3nm的表面的区域作为接触层，其中添加的氧的百分比为10％以上，而主沟道层的区域为以加入的氧气的百分比形成10％以下，形成多层结构。因此，相对于电极金属的欧姆特性和抑制阈值电位偏移的可靠性都可以兼容。版权所有（C）2010，JPO＆INPIT

15. 发明专利

JP2010021170A Semiconductor device, and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010021170A
公开(公告)日：2010-01-28
申请号：JP2008177550
申请日：2008-07-08
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KAWAMURA TETSUSHI , UCHIYAMA HIROYUKI , SAITO SHINICHI , WAKANA HIRONORI , HATANO MUTSUKO
IPC分类号： H01L29/786 , H01L21/28 , H01L21/336 , H01L27/00 , H01L29/417
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which includes an oxide TFT (Thin Film Transistor) having a channel layer of not larger than approximately 10 nm and operates at high speed by reducing contact resistance between the channel layer and a source electrode or between the channel layer and a drain electrode in the oxide TFT. SOLUTION: The oxide TFT is formed to be in a completely depleted state when OFF. Then a contact layer CTS is formed between the channel layer CHN and the source electrode ST, and a contact layer CTD is formed between the channel layer CHN and the drain electrode DT. Further, a ratio Cp/Cgi is smaller than 0.7, wherein Cgi is the gate insulating film capacitance between the gate electrode GT and the channel layer CHN, and Cp is the sum of parasitic capacitance between a structure other than the gate electrode GT and the channel layer CHN. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，其包括具有不大于约10nm的沟道层的氧化物TFT（薄膜晶体管），并且通过降低沟道层和源极之间的接触电阻而高速操作电极，或氧化物TFT中的沟道层和漏电极之间。解决方案：当OFF时，氧化物TFT形成为完全耗尽状态。然后在沟道层CHN和源电极ST之间形成接触层CTS，并且在沟道层CHN和漏电极DT之间形成接触层CTD。此外，比率Cp / Cgi小于0.7，其中Cgi是栅极电极GT和沟道层CHN之间的栅极绝缘膜电容，Cp是除栅极电极GT和栅极电极GT之外的结构之间的寄生电容之和通道层CHN。版权所有（C）2010，JPO＆INPIT

16. 发明专利

JP2009158663A Oxide semiconductor device and method of manufacturing the same 有权
标题翻译：氧化物半导体器件及其制造方法
公开(公告)号：JP2009158663A
公开(公告)日：2009-07-16
申请号：JP2007333865
申请日：2007-12-26
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： UCHIYAMA HIROYUKI
IPC分类号： H01L29/786 , H01L21/336 , H01L21/338 , H01L29/778 , H01L29/812
CPC分类号： H01L29/7869 , H01L27/1225
摘要： PROBLEM TO BE SOLVED: To solve the problem that reliability of a thin film transistor for display device cannot be obtained because of threshold potential shift and leakage current resulting from power feeding caused by missing oxygen at the interface between a zinc oxide system oxide semiconductor layer and a gate insulating film layer.
SOLUTION: Missing oxygen generated at the interface between the zinc oxide system oxide semiconductor and the gate insulating film is completed with a surface process using sulfur and celenium as the oxygen group elements rarely generating change in physical property values and compound of these elements. The missing oxygen can effectively be replaced with sulfur and celenium atoms to prevent generation of electron seizing sites only by conducting a gas phase or liquid phase process on the oxide semiconductor or gate insulating film without large alteration in the manufacturing process. As a result, threshold potential shift and leakage current in the thin film transistor characteristics can be controlled.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：为了解决由于氧化锌系氧化物之间的界面处缺氧而导致的阈值电位移动和由馈电引起的漏电电流而导致的显示装置用薄膜晶体管的可靠性不能得到的问题半导体层和栅极绝缘膜层。解决方案：氧化锌系氧化物半导体和栅极绝缘膜之间的界面产生的缺氧完成了使用硫和硅的表面方法作为氧基元素，很少会产生物理性能值的变化和这些元素的化合物。缺氧可以有效地被硫和硅原子代替，以防止在氧化物半导体或栅极绝缘膜上进行气相或液相处理而在制造过程中没有大的改变而产生电子捕获位点。结果，可以控制薄膜晶体管特性中的阈值电位移动和漏电流。版权所有（C）2009，JPO＆INPIT

17. 发明专利

JP2004063527A Semiconductor memory device and its manufacturing method 审中-公开
公开(公告)号：JP2004063527A
公开(公告)日：2004-02-26
申请号：JP2002216112
申请日：2002-07-25
申请人： Elpida Memory Inc , Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： OYU SHIZUNORI , OGISHIMA JUNJI , UCHIYAMA HIROYUKI , KAWAKITA KEIZO , SUZUKI MASATO
IPC分类号： H01L21/76 , H01L21/265 , H01L21/336 , H01L21/762 , H01L21/8234 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/76237 , H01L21/26586 , H01L21/823481 , H01L27/10873
摘要： PROBLEM TO BE SOLVED: To prevent the refreshing characteristics deteriorated by the influence of adjacent word lines of adjacent cells and to enable to reduce defects a after packaging and reflowing. SOLUTION: An active region 1 has a diffused layer in a region sandwiched between word lines 4, 2, 3 and 5. The diffused layer 6 sandwiched between the word lines 2 and 3 is connected to a bit line via a contact, and a diffused layer 7 sandwiched between the word lines 2 and 4 and a diffused layer 8 sandwiched between the word lines 3 and 5 are connected to respective capacities through a contact. A cell structure has two cell transistors in which the word line 2 is used as a gate electrode, and the diffused layers 6, 7 are used as source/drain. In the structure, the word line 3 is used as a gate electrode, and the diffused layers 6, 8 are used as source/drain. N-type diffused layers 7, 8 formed of the word lines 2, 3 adjacent to the word lines 4, 5 have a high n-type carrier concentration at the word lines 4, 5 sides from the word lines 2, 3 sides, or a p-type substrate concentration is set to a low concentration at the word lines 4, 5 sides. COPYRIGHT: (C)2004,JPO

18. 发明专利

JP2002151665A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREFOR 失效
公开(公告)号：JP2002151665A
公开(公告)日：2002-05-24
申请号：JP2000347096
申请日：2000-11-14
申请人： HITACHI LTD
发明人： ICHINOSE TERUYUKI , UCHIYAMA HIROYUKI , SUZUKI MASAYASU
IPC分类号： H01L21/3205 , H01L21/02 , H01L21/285 , H01L21/768 , H01L21/8242 , H01L23/522 , H01L27/10 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To prevent disconnection at micronizing of the width of wiring constituted, with a W film as a main component to be 0.1 μm or less. SOLUTION: On the inner side of a sidewall spacer 24, formed on the sidewall of a wiring groove 23, a bit line BL, composed of a conductive film whose main component is W (tungsten), is formed. A TiN film 25, whose adhesion to silicon oxide is stronger than W, is formed at the boundary of the bit line BL and the sidewall spacer 24 and functions as an adhesive layer preventing the boundary peeling of the bit line BL and the sidewall spacer 24.

19. 发明专利

JP2001077128A HIGH FREQUENCY MODULE 失效
公开(公告)号：JP2001077128A
公开(公告)日：2001-03-23
申请号：JP25247099
申请日：1999-09-07
申请人： HITACHI LTD
发明人： TAKATANI SHINICHIRO , TANIMOTO TAKUMA , HIGUCHI KATSUHIKO , UCHIYAMA HIROYUKI
IPC分类号： H01L23/12 , H01L21/338 , H01L29/778 , H01L29/80 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a high frequency module in millimeter wave band having excellent high-frequency characteristics where an MMIC(monolithic microwave integrated circuit) is mounted to improve the S/N ratio and reduce the source inductance. SOLUTION: As a basic element of an MMIC constituting a high frequency module, a distortion-relaxed HEMT(high electron mobility transistor) is used, where the substrate under an element region 3 is removed to expose a distortion- relaxed layer 2 in which fluorine is diffused with a rear-surface electrode 8 directly contacting it, while a minute via hole 7 is provided directly under a source electrode 4 for reduced source inductance. Thus, fluctuations in characteristics of element and low frequency noise due to carrier traps or charging/discharging, etc., at the defect level of the distortion-relaxed layer are suppressed, so that the S/N of MMIC is improved for a high frequency module and satisfactory high frequency characteristics are obtained.

20. 发明专利

JPH10242163A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH10242163A
公开(公告)日：1998-09-11
申请号：JP4523097
申请日：1997-02-28
申请人： HITACHI LTD
发明人： MOCHIZUKI KAZUHIRO , TAGAMI TOMONORI , HIGUCHI KATSUHIKO , UCHIYAMA HIROYUKI , GOSHIMA SHIGEO , TAKATANI SHINICHIRO
IPC分类号： H01L29/73 , H01L21/331 , H01L29/205 , H01L29/737
摘要： PROBLEM TO BE SOLVED: To increase the emitter grounded current amplification factor of a hetero-junction bipolar transistor by providing an emitter contact layer having a smaller area of its surface facing an emitter layer than a base-collector area and larger area of its opposite surface than this area and setting the thickness of the emitter layer within specified range. SOLUTION: A first emitter contact layer 2 is formed on a GaAs semiconductor substrate 1 and an etching stopper layer 3 and second emitter contact layer 4 and laminated. The second layer 4 has a truncated pyramid shape with a side face of (111) plane. The effective emitter area, i.e., the contact area of the contact layer 4 and emitter layer 5 is less than that of a base layer 6 and collector layer 8 and the opposite surface area to the emitter layers 5 is larger than this area and the emitter layer 5 has a thickness of 15-50nm.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式