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11. 发明专利

JPH01232441A PARITY COUNTING CIRCUIT 失效
公开(公告)号：JPH01232441A
公开(公告)日：1989-09-18
申请号：JP5887788
申请日：1988-03-11
申请人： FUJITSU LTD
发明人： KIMURA TERUO , TAKAHASHI YOSHITOSHI , ENDO TAKEMI , HENMI SATOSHI
IPC分类号： G06F11/10
摘要： PURPOSE:To securely count the parity of even fast data by resetting the output of a JK flip-flop at a frame period and using the output of the JK flip-flop right before resetting as a parity counting output. CONSTITUTION:Two sequences of data D1 and D2 which are inputted to an exclusive OR circuit 11 are obtained by dividing one sequence of original data into two sequences by series/parallel conversion, so the data speed is halved. Those sequences of data are inputted to an exclusive OR circuit 11 and ORed. The OR result data is in one sequence and inputted to the JK flip-flop 12, and its speed is 1/2. Consequently, the margin of reset pulses inputted to the JK flip-flop 12 is increased double and respective frames can be reset with the margin, so that the parity of even fast data can securely be counted.

12. 发明专利

JPS60146206A PREVENTING METHOD OF DISTURBANCE OPTICAL SIGNAL 失效
公开(公告)号：JPS60146206A
公开(公告)日：1985-08-01
申请号：JP308284
申请日：1984-01-10
申请人： FUJITSU LTD
发明人： ONO YOUKO , TANAKA YASUHIRO , YABE TOSHIHIRO , KIMURA TERUO
IPC分类号： G02B6/42
摘要： PURPOSE:To prevent a malfunction of a system caused by disturbance light, and to raise a transmission characteristic by cutting off a photodetector circuit at the time of non-coupling of a photodetector and a transmission line. CONSTITUTION:When a transmission line 2 is not inserted in a transmission line inserting hole 12 provided on an optical connector body 1, a light emitting element 4 connected to a power source 6 is provided on the inside surface of the inserting hole 12, and the light of the element 4 is detected by a photosensor 5. When the detected light of the sensor 5 is made incident on a comparator 7, a gate 9 does not operate due to a drop of an output voltage. When the line 2 is inserted into the hold 12, the light of the element 4 is not detected by the sensor 5, therefore, the output voltage of the comparator 7 becomes high. The light of the line 2 is photodetected by a photodetector 3 and converted to a voltage. This converted voltage is amplified by an amplifier 8 and inputted to the gate 9, the gate 9 is operated by the output voltage of the comparator 7, and it becomes an output signal and is transmitted.

13. 发明专利

JPH0151094B2 失效
公开(公告)号：JPH0151094B2
公开(公告)日：1989-11-01
申请号：JP17918084
申请日：1984-08-30
申请人： FUJITSU LTD
发明人： OOTSUKA MASANORI , KIMURA TERUO
IPC分类号： H03M7/14 , H04L25/49

14. 发明专利

JPS6165521A Reset signal generating circuit for logic circuit 失效
标题翻译：复位信号发生电路用于逻辑电路
公开(公告)号：JPS6165521A
公开(公告)日：1986-04-04
申请号：JP18602384
申请日：1984-09-05
申请人： Fujitsu Ltd
发明人： KIMURA TERUO
IPC分类号： H03K17/22
摘要： PURPOSE: To generate surely a reset signal even to a power supply interrupted at high speed by providing an integration consisting of a series circuit comprising a resistor and a capacitor between the power supply and a ground line, leading out a reset signal output terminal from a connecting point between the resistor and capacitor, providing a relay contact between the said output terminal and ground and connecting the output terminal to ground at power interruption to neutralize the electric charge in the capacitor.
CONSTITUTION: A resistor R and a capacitor C are connected between a power supply terminal 1 and an earth terminal 2. A reset pulse output terminal 3 is led out of a connecting point between the resistor and the capacitor. A relay contact γ is provided between the reset pulse output terminal 3 and ground. An exciting winding L is connected between a power supply and ground. The relay contact γ is a break contact and the contact is opened when power is applied. The electric charge of the capacitor C interrupting the power supply is neutralized rapidly by closing the relay contact γ and the output terminal voltage restores rapidly to ground potential.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：即使通过提供由电源和地线之间的电阻器和电容器组成的串联电路组成的积分，即使对高速中断的电源也可以产生复位信号，从而将复位信号输出端子从电阻和电容之间的连接点，在所述输出端子和地之间提供继电器触点，并且在断电时将输出端子连接到地，以中和电容器中的电荷。构成：在电源端子1和接地端子2之间连接有电阻R和电容器C.复位脉冲输出端3从电阻和电容之间的连接点引出。在复位脉冲输出端子3和地之间提供继电器触点伽马。励磁绕组L连接在电源和地之间。继电器触点gamma是断路触点，当接通电源时触点断开。中断电源的电容器C的电荷通过闭合继电器触点γ而迅速中和，并且输出端电压迅速恢复到地电位。

15. 发明专利

JPS6158326A Mbnb code converting circuit 失效
标题翻译： MBNB代码转换电路
公开(公告)号：JPS6158326A
公开(公告)日：1986-03-25
申请号：JP17918084
申请日：1984-08-30
申请人： Fujitsu Ltd
发明人： OTSUKA MASANORI , KIMURA TERUO
IPC分类号： H03M7/14 , H04L25/49
摘要： PURPOSE: To integrate devices by using an 1-chip gate array circuit, by respectively forming a serial-parallel converting section, mark rate detecting section, code converting section, code rule detecting section, selective output section, and parallel-serial converting section by using logical circuits.
CONSTITUTION: Input data DATA is added to a serial-parallel converting section 1 together with a clock signal CLK which is added to the converting section 1 as a converting timing signal after it is frequency-divided 7 into six parts of 1/6. Parallel output signals A0∼A5 of the converting section 1 are subjected to mark rate detection 2 and plural detected signals M3, M1, M2, and M4 of the mark rate are added to a selective output section 5. When the data DATA coincides with a code rule, signals D0∼D6 corresponding to the signals A1∼A5, A0, and A6 are selectively outputted from a selecting circuit 16 and subjected to parallel-serial conversion 6. After the conversion, the signals D0∼D6 are outputted through an FF 11. The signals D0∼D4 are outputted as bits, the signal D5 is outputted as an error bit, and the signal D6 becomes a status bit. Therefore, a 6-bit code can be converted into a 5-bit code by using the logical circuits.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过使用单芯片门阵列电路来集成器件，通过分别形成串并行转换部分，标记速率检测部分，代码转换部分，代码规则检测部分，选择输出部分和并行串行转换部分，通过使用逻辑电路。构成：输入数据DATA与时钟信号CLK一起被添加到串行/并行转换部分1中，时钟信号CLK被加到转换部分1之后，作为转换定时信号被分频成为1/6的六分之一。对转换部分1的并行输出信号A0-A5进行标记速率检测2，并且标记速率的多个检测信号M3，M1，M2和M4被添加到选择输出部分5.当数据DATA与代码规则，从选择电路16选择性地输出与信号A1-A5，A0和A6相对应的信号D0-D6并进行并行 - 串行转换6.转换后，通过FF输出信号D0-D6 信号D0-D4作为位输出，信号D5作为误差位输出，信号D6成为状态位。因此，可以通过使用逻辑电路将6位代码转换为5位代码。

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