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11. 发明专利

JP2014187419A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2014187419A
公开(公告)日：2014-10-02
申请号：JP2013059026
申请日：2013-03-21
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO MIKIHIKO , KOYANAGI MASARU , MASUDA MASAMI
IPC分类号： H03K5/125 , G11C11/407
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that ensures a sufficient margin in a high speed operation by suppressing a duty ratio deviation.SOLUTION: A first differential amplifier 11 charges first output ends OUTe, BOUTe with a second voltage different from a first voltage, stops charging the first output ends on a first clock signal clkeq, and receives first complementary data DTe, BDTe of a first voltage and outputs the first complementary data from the first output ends at a second voltage at a rise of a second clock signal clked. A second differential amplifier 12 charges second output ends with the second voltage, stops charging the second output ends OUTo, BOUTo on a third clock signal clkoq, and receives second complementary data DTo, BDTo of the first voltage and outputs the second complementary data from the second output ends at the second voltage at a rise of a fourth clock signal clkod.
摘要翻译：要解决的问题：提供通过抑制占空比偏差来确保高速运行中的足够余量的半导体器件。解决方案：第一差分放大器11用不同于第一电压的第二电压对第一输出端OUTe，BOUTe充电在第一时钟信号clkeq上停止对第一输出端充电，并且接收第一电压的第一互补数据DTe，BDTe，并且以第二电压在第二时钟信号的上升处输出来自第一输出端的第一互补数据。第二差分放大器12用第二电压对第二输出端充电，在第三时钟信号clkoq上停止对第二输出端OUTo，BOUTo充电，并接收第一电压的第二互补数据DTo，BDTo，并输出第二补偿数据第二输出在第四时钟信号clkod的上升沿第二电压结束。

12. 发明专利

JP2014103282A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2014103282A
公开(公告)日：2014-06-05
申请号：JP2012254753
申请日：2012-11-20
申请人： Toshiba Corp , 株式会社東芝
发明人： SUEMATSU YASUHIRO , KOYANAGI MASARU , ITO MIKIHIKO
IPC分类号： H01L21/8234 , H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/06 , H01L27/088 , H01L27/092
CPC分类号： H01L2224/48145 , H01L2224/48147 , H01L2225/06562
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that allows high-speed operation.SOLUTION: A semiconductor device includes: a pad connected to a first node; a first output buffer circuit including a first transistor having one end connected to the first node; a second node electrically connected to the first node; and a second output buffer circuit including a second transistor having one end electrically connected to the second node. The distance from a contact to a gate of the second transistor is shorter than the distance from a contact to a gate of the first transistor.
摘要翻译：要解决的问题：提供允许高速操作的半导体器件。解决方案：半导体器件包括：连接到第一节点的焊盘; 第一输出缓冲电路，包括具有连接到第一节点的一端的第一晶体管; 电连接到第一节点的第二节点; 以及第二输出缓冲电路，其包括具有电连接到第二节点的一端的第二晶体管。从第二晶体管的接触到栅极的距离比从第一晶体管的接触到栅极的距离短。

13. 发明专利

JP2012069198A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2012069198A
公开(公告)日：2012-04-05
申请号：JP2010212716
申请日：2010-09-22
申请人： Toshiba Corp , 株式会社東芝
发明人： MAEJIMA HIROSHI , ITO MIKIHIKO
IPC分类号： G11C16/06 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/10 , G11C16/30 , G11C16/32
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device capable of reducing an area of a pump which is a voltage supply source to a power source line, etc., and capable of mitigating stress of a switching circuit transferring the voltage to the power source line, etc.SOLUTION: The nonvolatile semiconductor memory device comprises: a cell array 11 arranged between a first area and a second area; first and second row decoders 12-0 arranged on the first area; a first power source line VRDEC_T arranged on the first area to transfer the voltage to the first row decoder; a second power source line VRDEC_B arranged on the first area to transfer the voltage to the second row decoder; a row system peripheral circuit 17 for supplying the voltage to the first and second power source lines; a first switch circuit SWV_T for switching between the first power source line and the circuit 17 to the connection state or cur-off state; and a second switch circuit SWV_B for switching between the second power source line and the circuit 17 to the connection state or cut-off state. At the writing operation, the first switch circuit makes between the first power source line and the circuit 17 to the connection state, and the second switch circuit makes between the second power source line and the circuit 17 to the cut-off state.
摘要翻译：解决的问题：提供一种非易失性半导体存储器件，其能够将作为电源线的泵的面积减小到电源线等，并且能够减轻转换电压的开关电路的应力电源线等。解决方案：非易失性半导体存储器件包括：布置在第一区域和第二区域之间的单元阵列11; 布置在第一区域上的第一和第二行解码器12-0; 布置在第一区域上以将电压传送到第一行解码器的第一电源线VRDEC_T <0> 布置在第一区域上以将电压传送到第二行解码器的第二电源线VRDEC_B <0> 用于向第一和第二电源线提供电压的行系统外围电路17; 用于在第一电源线和电路17之间切换到连接状态或截止状态的第一开关电路SWV_T0; 以及用于在第二电源线和电路17之间切换到连接状态或截止状态的第二开关电路SWV_B <0>。在写入操作时，第一开关电路在第一电源线和电路17之间形成连接状态，第二开关电路在第二电源线和电路17之间形成截止状态。版权所有（C）2012，JPO＆INPIT

14. 发明专利

JP2005267713A Dynamic type semiconductor memory device 审中-公开
标题翻译：动态型半导体存储器件
公开(公告)号：JP2005267713A
公开(公告)日：2005-09-29
申请号：JP2004076160
申请日：2004-03-17
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO MIKIHIKO , KOYANAGI MASARU
IPC分类号： G11C11/409 , G11C5/00 , G11C11/401
CPC分类号： G11C7/1018 , G11C7/1069 , G11C7/1096 , G11C11/4045 , G11C11/4076 , G11C11/4093 , G11C11/4097
摘要： PROBLEM TO BE SOLVED: To achieve the high speed of continuous column access in a dynamic type semiconductor memory device while suppressing an increase in chip size to a minimum.
SOLUTION: This device is provided with first and second memory cell groups to be divided based on column addresses, a first bit line connected to the first memory cell group, a second bit line connected to the second memory cell group, first and second local data lines, a column selecting means for connecting the first and second bit lines to the first and second local data lines based on the column addresses, first and second master data lines, a local data line selecting means for connecting the first and second local lines to the first and second master data lines, a DRB for reading data from the first or second master data line, and a DWB for writing data in the first or second master data line.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了在动态类型的半导体存储器件中实现高速连续列存取，同时将芯片尺寸的增加抑制到最小。解决方案：该设备提供有第一和第二存储单元组，其将基于列地址被划分，第一位线连接到第一存储单元组，第二位线连接到第二存储单元组，第一和第第二本地数据线，列选择装置，用于基于列地址将第一和第二位线连接到第一和第二本地数据线，第一和第二主数据线，用于连接第一和第二本地数据线的本地数据线选择装置到第一和第二主数据线的本地线，用于从第一或第二主数据线读取数据的DRB和用于在第一或第二主数据线中写入数据的DWB。版权所有（C）2005，JPO＆NCIPI

15. 发明专利

JP2013183072A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013183072A
公开(公告)日：2013-09-12
申请号：JP2012046627
申请日：2012-03-02
申请人： Toshiba Corp , 株式会社東芝
发明人： SUEMATSU YASUHIRO , KOYANAGI MASARU , ITO MIKIHIKO
IPC分类号： H01L21/822 , H01L27/04
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that allows preventing a reduction in propagation speed of a signal due to a protection circuit and allows high speed operation.SOLUTION: A first semiconductor chip 21 receives a signal from the outside, and has a first input pad connected to a first internal circuit and a first protection circuit protecting the first internal circuit. At least one second semiconductor chips 22 to 28 are stacked on the first semiconductor chip, receive a signal from the outside, have a second input pad connected to a second internal circuit and a second protection circuit protecting the second internal circuit. First connection means 29 electrically connects the first input pad and the second input pad. Second connection means 21f connects the first protection circuit of the first semiconductor chip and the first input pad. The second protection circuits of the at least one second semiconductor chips are not connected to the second input pad.
摘要翻译：要解决的问题：提供一种半导体装置，其能够防止由保护电路引起的信号的传播速度的降低，并允许高速运行。解决方案：第一半导体芯片21从外部接收信号，并且具有第一连接到第一内部电路的输入焊盘和保护第一内部电路的第一保护电路。至少一个第二半导体芯片22至28堆叠在第一半导体芯片上，从外部接收信号，具有连接到第二内部电路的第二输入焊盘和保护第二内部电路的第二保护电路。第一连接装置29电连接第一输入焊盘和第二输入焊盘。第二连接装置21f连接第一半导体芯片的第一保护电路和第一输入焊盘。至少一个第二半导体芯片的第二保护电路不连接到第二输入焊盘。

16. 发明专利

JP2012216265A Input circuit 有权
标题翻译：输入电路
公开(公告)号：JP2012216265A
公开(公告)日：2012-11-08
申请号：JP2011081064
申请日：2011-03-31
申请人： Toshiba Corp , 株式会社東芝
发明人： KOYANAGI MASARU , ITO MIKIHIKO
IPC分类号： G11C16/06
CPC分类号： H03K19/017527
摘要： PROBLEM TO BE SOLVED: To allow an input signal to be loaded at appropriate timing.SOLUTION: A first input circuit 10 detects an input signal IO and outputs a first output signal Din that is in-phase with the input signal IO. A second input circuit 20 detects a first strobe signal DQS and outputs a second output signal /DQSi. A third input circuit 30 detects a second strobe signal BDQS generated by inverting the first strobe signal DQS and outputs a third output signal /BDQSi. A data latch circuit 70 includes a first latch circuit L1 and a second latch circuit L2, and causes one of either the first latch circuit L1 or the second latch circuit L2 to latch the first output signal Din and permits the first output signal Din to be input to the other of either the first latch circuit L1 or the second latch circuit L2, based on the first output signal Din, the second output signal /DQSi and the third output signal /BDQSi.
摘要翻译：要解决的问题：允许在适当的时间加载输入信号。解决方案：第一输入电路10检测输入信号IO并输出与输入信号IO同相的第一输出信号Din。第二输入电路20检测第一选通信号DQS并输出第二输出信号DQSi。第三输入电路30检测通过反相第一选通信号DQS产生的第二选通信号BDQS，并输出第三输出信号/ BDQSi。数据锁存电路70包括第一锁存电路L1和第二锁存电路L2，并且使第一锁存电路L1或第二锁存电路L2中的任一个锁存第一输出信号Din，并使第一输出信号Din为基于第一输出信号Din，第二输出信号/ DQSi和第三输出信号/ BDQSi输入到第一锁存电路L1或第二锁存电路L2中的另一个。版权所有（C）2013，JPO＆INPIT

17. 发明专利

JP2008140914A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2008140914A
公开(公告)日：2008-06-19
申请号：JP2006324474
申请日：2006-11-30
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO MIKIHIKO , KOYANAGI MASARU
IPC分类号： H01L23/50
CPC分类号： H01L23/4951 , H01L23/49541 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48247 , H01L2224/49171 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/07802 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： PROBLEM TO BE SOLVED: To provide a technique for suppressing a performance decline due to the internal wiring resistance of a semiconductor chip and simplifying the routing of lead wires from a lead frame on which the semiconductor chip is mounted. SOLUTION: A semiconductor device includes a first inner lead 1 for grounding or source voltage which is formed inside a lead frame 10, and a semiconductor chip 5 which is mounted on the lead frame 10 and has a first pad for grounding or source voltage that is formed along a first side A. The first inner lead 10 has a first wiring portion extending in a direction parallel with the first side A. The first side A is so arranged as to vertically overlap the first wiring portion, and the first pad is connected to the first wiring portion. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种抑制由于半导体芯片的内部布线电阻引起的性能下降的技术，并且简化了从安装有半导体芯片的引线框架引线的布线。解决方案：半导体器件包括形成在引线框架10内部的用于接地或源极电压的第一内部引线1和安装在引线框架10上并具有用于接地或源极的第一焊盘的半导体芯片5 电压沿着第一侧A形成。第一内引线10具有沿与第一侧A平行的方向延伸的第一布线部。第一侧A被布置为与第一布线部垂直重叠，并且第一布线部垫连接到第一布线部分。版权所有（C）2008，JPO＆INPIT

18. 发明专利

JP2008011649A Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：JP2008011649A
公开(公告)日：2008-01-17
申请号：JP2006180148
申请日：2006-06-29
申请人： Toshiba Corp , Toshiba Microelectronics Corp , 東芝マイクロエレクトロニクス株式会社 , 株式会社東芝
发明人： SUEMATSU YASUHIRO , KIMURA TORU , KOYANAGI MASARU , YOSHIHARA MASAHIRO , ITO MIKIHIKO
IPC分类号： H02M3/07 , G11C11/4074 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device for reducing the size of the device as a whole, and efficiently boosting a power supply voltage.
SOLUTION: The semiconductor integrated circuit device is provided with: a first charge pump circuit CP1 for boosting power supply potential Vcc to first boost potential VPPS higher than the power supply potential; a pulse generator PG2 for receiving the first boost potential, and outputting a pulse signal at the first boost potential; and a second charge pump circuit CP2 including a capacitor Cpw for receiving the pulse at the first boost potential, and boosting the power supply potential to second boost potential VPPW higher than the first boost potential.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于整体减小器件尺寸的半导体集成电路器件，并有效地提高电源电压。解决方案：半导体集成电路器件设置有：第一电荷泵电路CP1，用于将电源电位Vcc升高至高于电源电位的第一升压电位VPPS; 脉冲发生器PG2，用于接收第一升压电位，并输出第一升压电位的脉冲信号; 以及第二电荷泵电路CP2，其包括用于接收第一升压电位的脉冲的电容器Cpw，并将电源电位升高到高于第一升压电位的第二升压电位VPPW。版权所有（C）2008，JPO＆INPIT

19. 发明专利

JP2006093609A Semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：JP2006093609A
公开(公告)日：2006-04-06
申请号：JP2004280055
申请日：2004-09-27
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO MIKIHIKO , KOYANAGI MASARU
IPC分类号： H01L27/04 , H01L21/822
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which can reliably protect an internal circuit having a low voltage resistance by reducing a wiring resistance without involving increase of a width of a power wiring line.
SOLUTION: The semiconductor integrated circuit comprises a semiconductor substrate 5 of a first conduction type (p type); first, second, third semiconductor regions 201, 101, 102, 202 of the second conduction type (n type)and a substrate contact region 208 of a p
+ type, located adjacent to each other on the substrate 5; a first protecting transistor Tr
1 integrated on the first semiconductor region 201, first and second anode regions 108, 112 of the p
+ type located respectively on the second and third semiconductor regions 101 and 102; and first, second, third, and fourth contact regions 203, 105, 111, 207 of an n
+ type located respectively on first, second, third, and fourth semiconductor regions 201, 101, 102, 202.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种半导体集成电路，其可以通过降低布线电阻而可靠地保护具有低电压电阻的内部电路，而不会增加电力布线的宽度。解决方案：半导体集成电路包括第一导电类型（p型）的半导体衬底5; 第二导电类型（n型）的第一，第二，第三半导体区域201,101,102,202以及基板5上彼此相邻定位的基本接触区域208 ; 集成在第一半导体区域201上的第一保护晶体管Tr 1，分别位于第二和第三半导体区域上的p + 型的第一和第二阳极区域108,112 101和102; 以及分别位于第一，第二，第三和第四半导体区域201,101,102,202上的n + / SP>型的第一，第二，第三和第四接触区域203,105,111,207 （C）2006年，JPO＆NCIPI

20. 发明专利

JP2000182374A DYNAMIC SEMICONDUCTOR MEMORY 失效
公开(公告)号：JP2000182374A
公开(公告)日：2000-06-30
申请号：JP35909398
申请日：1998-12-17
申请人： TOSHIBA CORP
发明人： ITO MIKIHIKO , HARA TAKAHIKO
IPC分类号： G11C11/409 , G11C11/401 , G11C29/00 , G11C29/04
摘要： PROBLEM TO BE SOLVED: To reduce power consumption at the time of standby by reducing a pattern area of a bit line pre-charge equalizing circuit of a DRAM and reducing a leak current made to flow toward a word line of a short-circuited defective part between a word line and a bit line from a pre-charge power source line. SOLUTION: This memory is provided with plural cell array selecting switches 14 selecting plural memory cell arrays, a bit line sense amplifier 16 provided corresponding to pairs of bit line (BLL, bBLL), (BLR, bBLR) of plural memory cell arrays and connected to the pairs of bit line through the cell array selecting switch, a pre-charge equalizing circuit 15 connected to a pre-charge power source line 40 and the bit line sense amplifier 16 and pre-charging/ equalizing the selected pairs of bit line, and a current limiting element Q20 inserted between the pre-charge equalizing circuit 15 and the pre-charge power source line.

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