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131. 发明专利

JP2011060824A Substrate for mounting semiconductor chip, and method for producing the same 有权
标题翻译：用于安装半导体芯片的基板及其制造方法
公开(公告)号：JP2011060824A
公开(公告)日：2011-03-24
申请号：JP2009205856
申请日：2009-09-07
申请人： Hitachi Chem Co Ltd , 日立化成工業株式会社
发明人： EJIRI YOSHINORI , HASEGAWA KIYOSHI , SAKURAI TAKEHISA , TSUBOMATSU YOSHIAKI
IPC分类号： H01L23/12 , H05K3/46
CPC分类号： H05K3/244 , H01L21/4857 , H01L2924/00013 , H01L2924/0002 , H05K3/062 , H05K3/108 , H05K3/4644 , H05K3/4652 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a method for producing a substrate for mounting a semiconductor chip, in which the formation of bridges can be reduced and excellent wire bonding performance and solder joint reliability can be achieved even in forming fine wiring. SOLUTION: The method for producing a substrate for mounting a semiconductor chip includes: a resist forming step for forming resist 4 on a first copper layer 32 of a laminate in regions other than a region to be a conductor circuit 50, wherein the laminate has an inner layer plate 1 having an inner layer circuit 102 on the surface thereof and the first copper layer 32 formed on the inner layer plate 1 with an insulating layer 21 therebetween; a conductor circuit forming step for obtaining the conductor circuit 50 by forming a second copper layer 5 on the first copper layer 32 by electrolytic copper plating; a nickel layer forming step for forming a nickel layer on at least a part of the conductor circuit 50 by electrolytic nickel plating; a resist removing step for removing the resist 4; an etching step for removing the first copper layer 32 by etching; and a gold layer forming step for forming a gold layer on at least a part of the conductor circuit 50 by electroless gold plating. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：提供一种用于制造用于安装半导体芯片的基板的方法，其中即使在形成精细布线时也可以实现桥接的形成，并且即使在形成精细布线时也可以实现优良的引线接合性能和焊点可靠性。解决方案：用于制造用于安装半导体芯片的基板的方法包括：抗蚀剂形成步骤，用于在除了作为导体电路50的区域之外的区域中的层叠体的第一铜层32上形成抗蚀剂4，其中层叠体具有在其表面上具有内层电路102的内层板1和形成在内层板1上的第一铜层32，其间具有绝缘层21; 导体电路形成步骤，用于通过电解镀铜在第一铜层32上形成第二铜层5来获得导体电路50; 镍层形成步骤，用于通过电解镀镍在导体电路50的至少一部分上形成镍层; 用于去除抗蚀剂4的抗蚀剂去除步骤; 用于通过蚀刻去除第一铜层32的蚀刻步骤; 以及通过无电镀金在导体电路50的至少一部分上形成金层的金层形成工序。版权所有（C）2011，JPO＆INPIT

132. 发明专利

JP2011049530A Method of manufacturing semiconductor device, and semiconductor device 有权
标题翻译：制造半导体器件的方法和半导体器件
公开(公告)号：JP2011049530A
公开(公告)日：2011-03-10
申请号：JP2010143085
申请日：2010-06-23
申请人： Toshiba Corp , 株式会社東芝
发明人： YAMASHITA SOICHI , UDA TATSUO , IIJIMA TADASHI , MIYATA MASAHIRO , UCHIDA MASAYUKI , TOGASAKI TAKASHI , EZAWA HIROKAZU
IPC分类号： H01L23/12 , H01L21/60
CPC分类号： H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/16 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/81 , H01L2224/02311 , H01L2224/02381 , H01L2224/0401 , H01L2224/04042 , H01L2224/05008 , H01L2224/05548 , H01L2224/05569 , H01L2224/05571 , H01L2224/05572 , H01L2224/05666 , H01L2224/0603 , H01L2224/06051 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13083 , H01L2224/13099 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2224/2919 , H01L2224/32145 , H01L2224/45144 , H01L2224/48666 , H01L2224/73204 , H01L2224/73207 , H01L2224/73215 , H01L2224/81191 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/05552 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, the method forming two types of terminals different in forms by a simple process. SOLUTION: In this method of manufacturing a semiconductor device, a photosensitive resin film is formed on a substrate W1 on which an electrode terminal comprising a first conductive layer 11 is provided, and is exposed to light and developed to form first and second openings reaching the electrode terminal; the photosensitive resin film is baked to be altered to an insulating layer 14; a second conductive layer 17 connected to the electrode terminal is formed on the insulating layer 14 including the first opening; a third conductive layer 18, having an oxidation-reduction potential of which the difference from that of the first conductive layer 11 is smaller than a difference of the oxidation-reduction potential between the first conductive layer 11 and the second conductive layer 17, is formed on the second conductive layer 17; a photosensitive resin film is formed on the substrate W1, and exposed to light and developed to form a third opening 13d reaching the third conductive layer 18 and a fourth opening 13e reaching the electrode terminal via the second opening; and the photosensitive resin film is baked to be modified to an insulating layer 19 to form a bump connected to the third conductive layer 18. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种制造半导体器件的方法，该方法通过简单的工艺形成形式不同的两种类型的端子。解决方案：在这种制造半导体器件的方法中，在设置有包括第一导电层11的电极端子的基板W1上形成感光性树脂膜，并将其曝光并显影以形成第一和第二开口到达电极端子; 感光性树脂膜被烘烤改变为绝缘层14; 连接到电极端子的第二导电层17形成在包括第一开口的绝缘层14上; 形成具有与第一导电层11的差异小于第一导电层11和第二导电层17之间的氧化还原电位差的氧化还原电位的第三导电层18 在第二导电层17上; 在基板W1上形成感光性树脂膜，曝光并显影，形成到达第三导电层18的第三开口13d和经由第二开口到达电极端子的第四开口13e; 并且将感光性树脂膜进行烘烤以改性为绝缘层19，以形成连接到第三导电层18的凸块。（C）2011，JPO＆INPIT

133. 发明专利

JP2011044496A Semiconductor device and semiconductor apparatus using the same 审中-公开
标题翻译：使用相同的半导体器件和半导体器件
公开(公告)号：JP2011044496A
公开(公告)日：2011-03-03
申请号：JP2009190385
申请日：2009-08-19
申请人： Panasonic Corp , パナソニック株式会社
发明人： NAKANO SUMIAKI
IPC分类号： H01L21/60 , H01L21/3205 , H01L23/52
CPC分类号： H01L24/11 , H01L23/3192 , H01L24/13 , H01L2224/03828 , H01L2224/0401 , H01L2224/05015 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05155 , H01L2224/05555 , H01L2224/05559 , H01L2224/05572 , H01L2224/05644 , H01L2224/06131 , H01L2224/11334 , H01L2224/1146 , H01L2224/11849 , H01L2224/13005 , H01L2224/13006 , H01L2224/13007 , H01L2224/13014 , H01L2224/13017 , H01L2224/13021 , H01L2224/13023 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/00014 , H01L2924/2075 , H01L2924/2076 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which is highly reliable by improving bonding strength over the entire interface of a bump, an under barrier metal, etc., and a semiconductor apparatus using the same.
SOLUTION: The semiconductor device includes an electrode pad 4 formed on a substrate 5, a first protective film 3 formed on the substrate 5 and electrode pad 4 and having a first opening for exposing the electrode pad 4, the under barrier metal 2 formed on the electrode pad 4 so as to cover a peripheral edge of the first opening of the first protective film 3, and the bump 6 formed on the under barrier metal 2. Here, an angle of contact between the under barrier metal 2 and the first protective film 3 at the peripheral edge of the under barrier metal 2 is ≤90°, and an angle of contact between the bump 6 and under barrier metal 2 at the peripheral edge of the bump 6 is ≤90°.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：提供通过提高凸块，下阻挡金属等的整个界面上的接合强度以及使用其的半导体装置来提供高可靠性的半导体器件。解决方案：半导体器件包括形成在基板5上的电极焊盘4，形成在基板5上的第一保护膜3和电极焊盘4，并具有用于暴露电极焊盘4的第一开口，下阻挡金属2 形成在电极焊盘4上，以覆盖第一保护膜3的第一开口的周边边缘和形成在下阻挡金属2上的突起6.这里，下阻挡金属2与在下阻挡金属2的周缘处的第一保护膜3为≤90°，突起6与阻挡金属2之间在凸块6的周缘处的接触角为≤90°。版权所有（C）2011，JPO＆INPIT

134. 发明专利

JP2011026595A Protection tape for plating 审中-公开
标题翻译：镀层保护胶带
公开(公告)号：JP2011026595A
公开(公告)日：2011-02-10
申请号：JP2010166079
申请日：2010-07-23
申请人： Sekisui Chem Co Ltd , 積水化学工業株式会社
发明人： SUGITA TAIHEI , SUMII YUICHI , MURAYAMA HIROSHI
IPC分类号： C09J7/02 , C09J4/02 , C09J11/06 , C09J133/08 , C09J133/10 , C09J201/00
CPC分类号： C25D5/022 , C09J7/20 , C09J2203/31 , C09J2203/326 , C23C18/1605 , H01L21/6836 , H01L2221/68372 , H01L2221/68381 , H01L2924/00013 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
摘要： PROBLEM TO BE SOLVED: To provide a protection tape for plating, which is capable of preventing occurrence of plating failure and can be easily removed after being used.
SOLUTION: The protection tape for plating to protect a non-plating surface when plating by an electroless plating method or an electrolytic plating method includes a base, and an adhesive layer containing a photo-curable resin, and a photopolymerization initiator, that is formed on at least one surface of the base wherein the photopolymerization initiator has a hydroxy group at its molecular end.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够防止电镀故障的发生的电镀保护带，并且可以在使用后容易地除去。解决方案：通过无电镀方法或电镀方法进行电镀时，用于电镀保护非电镀表面的保护带包括基体和含有光固化树脂的粘合剂层和光聚合引发剂，其中形成在基材的至少一个表面上，其中光聚合引发剂在其分子末端具有羟基。版权所有（C）2011，JPO＆INPIT

135. 发明专利

JP2011023484A Light emitting device 有权
标题翻译：发光装置
公开(公告)号：JP2011023484A
公开(公告)日：2011-02-03
申请号：JP2009166054
申请日：2009-07-14
申请人： Nichia Corp , 日亜化学工業株式会社
发明人： SUZUKI AKIRA , HAYASHI TADAO , TSUKIOKA TOMOYA , TAKEUCHI YOSHIKAZU
IPC分类号： H01L21/60 , H01L23/12 , H01L33/48
CPC分类号： H01L33/38 , H01L24/05 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/83 , H01L33/62 , H01L2224/0401 , H01L2224/04026 , H01L2224/05552 , H01L2224/0556 , H01L2224/05599 , H01L2224/06051 , H01L2224/16 , H01L2224/32225 , H01L2224/83192 , H01L2224/83194 , H01L2224/83801 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/01056 , H01L2924/01058 , H01L2924/01063 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12035 , H01L2924/12041 , H01L2924/12042 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/29099 , H01L2224/29599 , H01L2924/3512 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a light emitting device for reliably performing self-alignment even when electrodes on the side of a substrate are formed by separation with respect to one element to be mounted, and also suppressing a solder ball and the void of the electrode. SOLUTION: The light emitting device 1 is configured to face a rectangular element 10 and be mounted upon a mounting substrate via a heat-melted connecting material. In the device, second substrate electrodes 3 are formed in alignment with the recessed notches 2c of a first substrate electrode 2 and a portion of the outer periphery of the first and second substrate electrodes includes first extended sections 2b that extend farther outward than the outer periphery gs of the element. The first extending sections are formed in at least one or more locations on one side of the outer periphery of the rectangular element; the first substrate electrode includes second extending sections 2d that are formed on at least one of both ends of the recessed notches in alignment with the first extending sections of the second substrate electrodes; and the second extending sections extend farther outward than the outer periphery of the element. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种用于可靠地执行自对准的发光装置，即使通过相对于一个要安装的元件分离形成基板一侧的电极，并且还抑制焊球和无电极。解决方案：发光器件1被配置为面对矩形元件10并且经由热熔融连接材料安装在安装基板上。在该器件中，第二衬底电极3形成为与第一衬底电极2的凹陷凹槽2c对齐，并且第一和第二衬底电极的外周部分包括比外周更向外延伸的第一延伸部分2b 元素的gs。所述第一延伸部形成在所述矩形元件的外周的一侧的至少一个以上的位置; 第一基板电极包括第二延伸部分2d，其形成在与第二基板电极的第一延伸部分对准的凹陷部分的两端中的至少一个上; 并且所述第二延伸部分比所述元件的外周向外延伸得更远。版权所有（C）2011，JPO＆INPIT

136. 发明专利

JP2010267641A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2010267641A
公开(公告)日：2010-11-25
申请号：JP2009115198
申请日：2009-05-12
申请人： Panasonic Corp , パナソニック株式会社
发明人： TSUJIMOTO SHINYA
IPC分类号： H01L21/60
CPC分类号： H01L23/3171 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02125 , H01L2224/0401 , H01L2224/05027 , H01L2224/05557 , H01L2224/05559 , H01L2224/05562 , H01L2224/05572 , H01L2224/10126 , H01L2224/1132 , H01L2224/11334 , H01L2224/11849 , H01L2224/13006 , H01L2224/13021 , H01L2224/13023 , H01L2224/73204 , H01L2924/00013 , H01L2924/0002 , H01L2924/01006 , H01L2924/01029 , H01L2924/14 , H01L2924/351 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To prevent deterioration in a bump connection part caused by the difference in the thermal expansion ratio between a chip material and a circuit wiring board material, without fail, in a semiconductor device of flip-chip packaging. SOLUTION: An insulating film 111 is formed on a semiconductor substrate 101 so as to cover an end of an electrode pad 102 formed on the semiconductor substrate 101. A UBM 113 is formed on the electrode pad 102. A coarse surface structure 111a is formed on the surface part of the insulating film 111 of a part positioned on the end of the electrode pad 102. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了防止在芯片材料和电路布线板材料之间的热膨胀率的差异引起的凸块连接部分的劣化，在倒装芯片封装的半导体器件中。解决方案：在半导体衬底101上形成绝缘膜111，以覆盖形成在半导体衬底101上的电极焊盘102的端部。在电极焊盘102上形成UBM 113.粗糙表面结构111a 形成在位于电极焊盘102的端部的部分的绝缘膜111的表面部分上。版权所有（C）2011，JPO＆INPIT

137. 发明专利

JP2010212575A Method for manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2010212575A
公开(公告)日：2010-09-24
申请号：JP2009059185
申请日：2009-03-12
申请人： Casio Computer Co Ltd , カシオ計算機株式会社
发明人： WAKIZAKA SHINJI
IPC分类号： H01L23/12
CPC分类号： H01L24/11 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/14 , H01L2224/0401 , H01L2224/05001 , H01L2224/05022 , H01L2224/05023 , H01L2224/05027 , H01L2224/05082 , H01L2224/05111 , H01L2224/05124 , H01L2224/05147 , H01L2224/05553 , H01L2224/05555 , H01L2224/05571 , H01L2224/05647 , H01L2224/0603 , H01L2224/06131 , H01L2224/1132 , H01L2224/11472 , H01L2224/11849 , H01L2224/13013 , H01L2224/13014 , H01L2224/13023 , H01L2224/131 , H01L2224/1403 , H01L2224/14131 , H01L2224/94 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/00014 , H01L2224/11 , H01L2924/01014 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which forms solder bumps only on columnar electrodes by printing solder paste layers on the columnar electrodes by being shifted, suppresses generation of a void in the solder bump, and reduces a planar size.
SOLUTION: Solder paste layers 12a are printed on all columnar electrodes 10 arranged in a matrix-like form by being respectively shifted in appropriate directions instead of being printed by being shifted in the same direction. For instance, in a semiconductor device formation region surrounded by dicing streets 22, the solder paste layers 12a printed corresponding to the columnar electrodes 10 nearest to the right and left dicing streets 22 are printed at positions shifted to the center side in the horizontal direction of the semiconductor device formation region. Thereby, the solder paste layers 12a can be prevented from protruding to the outside of the dicing streets 22, and the planar size of the semiconductor device can be reduced.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造半导体器件的方法，该半导体器件仅在柱状电极上形成焊料凸块，通过移动在柱状电极上印刷焊膏层，抑制焊料凸块中的空隙的产生，并且减小平面尺寸解决方案：焊膏层12a印刷在以矩阵状形式布置的所有柱状电极10上，通过分别在适当的方向上偏移而不是通过沿相同方向移动来印刷。例如，在由切割街道22围绕的半导体器件形成区域中，对应于最靠近右侧和右侧切割街道22的柱状电极10印刷的焊膏层12a被印刷在向水平方向的中心侧移动的位置半导体器件形成区域。由此，可以防止焊膏层12a向切割街道22的外侧突出，能够降低半导体装置的平面尺寸。版权所有（C）2010，JPO＆INPIT

138. 发明专利

JP2010157703A Structure and method for improving solder bump connection in semiconductor device 有权
标题翻译：用于改善半导体器件中的焊接保护连接的结构和方法
公开(公告)号：JP2010157703A
公开(公告)日：2010-07-15
申请号：JP2009271304
申请日：2009-11-30
申请人： Internatl Business Mach Corp , インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation
发明人： DAUBENSPECK TIMOTHY HARRISON , GAMBINO JEFFREY P , SAUTER WOLFGANG , MUZZY CHRISTOPHER DAVID , SULLIVAN TIMOTHY DOOLING
IPC分类号： H01L21/60
CPC分类号： H01L24/05 , H01L23/3192 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/03452 , H01L2224/0401 , H01L2224/05017 , H01L2224/05019 , H01L2224/05027 , H01L2224/05088 , H01L2224/05096 , H01L2224/05098 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05564 , H01L2224/05568 , H01L2224/05647 , H01L2224/05671 , H01L2224/13006 , H01L2224/13023 , H01L2224/13111 , H01L2224/16238 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01093 , H01L2924/01327 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/30105 , H01L2924/01028 , H01L2924/00014 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552
摘要： PROBLEM TO BE SOLVED: To provide structures with improved solder bump connections that prevent cracking and peeling, and to provide a method of fabricating such structures.
SOLUTION: The method includes steps of: forming an upper wiring layer in dielectric layers 10, 20 and 22; and depositing one or more dielectric layers on the upper wiring layer. The method further includes a step of forming a plurality of discrete trenches in the one or more dielectric layers extending to the upper wiring layer. The method further includes a step of depositing a ball limiting metallurgy or under bump metallurgy in the plurality of discrete trenches to form discrete metal islands in contact with the upper wring layer. A solder bump is formed in electrical connection to the plurality of the discrete metal islands.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供具有改善的防止开裂和剥离的焊料凸块连接的结构，并提供制造这种结构的方法。解决方案：该方法包括以下步骤：在电介质层10,20和22中形成上布线层; 以及在所述上布线层上沉积一个或多个介电层。该方法还包括在延伸到上布线层的一个或多个介电层中形成多个离散沟槽的步骤。该方法还包括在多个离散的沟槽中沉积限界金属冶金或凸块下的冶金以形成与上部绞合层接触的离散的金属岛的步骤。形成与多个离散金属岛电连接的焊料凸块。版权所有（C）2010，JPO＆INPIT

139. 发明专利

JP2010129916A Substrate for mounting device, method for manufacturing the same, semiconductor module, and portable apparatus 有权
标题翻译：用于安装设备的基板，其制造方法，半导体模块和便携式设备
公开(公告)号：JP2010129916A
公开(公告)日：2010-06-10
申请号：JP2008305495
申请日：2008-11-28
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： SAITO KOICHI , YAMAMOTO TETSUYA
IPC分类号： H01L23/12
CPC分类号： H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02319 , H01L2224/02331 , H01L2224/02351 , H01L2224/02377 , H01L2224/0311 , H01L2224/0312 , H01L2224/03436 , H01L2224/0361 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/05647 , H01L2224/1132 , H01L2224/11849 , H01L2224/131 , H01L2224/94 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/351 , H01L2924/00014 , H01L2224/11 , H01L2224/03 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To improve reliability of connection between a bump electrode and a device electrode in a semiconductor module having a structure that the bump electrode formed on a wiring layer is connected to the device electrode formed on a semiconductor device. SOLUTION: An insulating resin layer 40 is formed between the semiconductor device 20 and the wiring layer 50. The bump electrode 60 formed integrally with the wiring layer 50 and protruded from the wiring layer 50 to the insulating resin layer 40 side is electrically connected to the device electrode formed on the semiconductor device 20. The height of a part of the wiring layer 50 on the end side of a protrusion connection area 52 is lower than the height of the wiring layer 50 in a wiring area 54 extended to the opposite side of the end side. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提高具有将形成在布线层上的突起电极连接到形成在半导体器件上的器件电极的结构的半导体模块中的凸块电极和器件电极之间的连接可靠性。解决方案：在半导体器件20和布线层50之间形成绝缘树脂层40.与布线层50一体形成并从布线层50突出到绝缘树脂层40侧的突起电极60是电连接到形成在半导体器件20上的器件电极。突起连接区域52的端侧的布线层50的一部分的高度比延伸到半导体器件20的布线区域54中的布线层50的高度低。端面的相对侧。版权所有（C）2010，JPO＆INPIT

140. 发明专利

JP2010129716A Semiconductor device and connection checking method for semiconductor device 有权
标题翻译：半导体器件的半导体器件和连接检查方法
公开(公告)号：JP2010129716A
公开(公告)日：2010-06-10
申请号：JP2008301888
申请日：2008-11-27
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： AKIYAMA NAOTO , UMESHIMA TOSHIAKI
IPC分类号： H01L23/12
CPC分类号： H01L25/0657 , H01L22/32 , H01L23/3142 , H01L23/49816 , H01L24/05 , H01L24/17 , H01L24/49 , H01L2224/0401 , H01L2224/05573 , H01L2224/05599 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/1705 , H01L2224/32225 , H01L2224/49174 , H01L2224/73204 , H01L2224/85399 , H01L2225/06513 , H01L2924/00013 , H01L2924/00014 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/29099 , H01L2224/29599 , H01L2924/014 , H01L2224/45015 , H01L2924/207 , H01L2924/00012 , H01L2224/45099 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which a connection between connection terminals and land of the semiconductor device can be checked with the semiconductor device kept in a sound condition, the connection not being allowed to be checked with a semiconductor chip. SOLUTION: The semiconductor device 1 includes: a package substrate 2; a semiconductor chip 3 mounted on the package substrate 2; a first land 210 formed in a first principal surface of the package substrate 2; a second land 211 formed in a second principal surface of the package substrate 2; first connection terminals 213 connected to the second land 211 and having the connection thereto not allowed to be checked with the semiconductor chip 3; a connection interconnection 212 for connecting the first land 210 and the second land 211; a second connection terminal 222 formed in the second principal surface of the package substrate 2; and a branch interconnection 221 for connecting the connection interconnection 212 and the second connection terminal 222. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供半导体器件，其中半导体器件的连接端子和焊盘之间的连接可以被保持在声音状态的半导体器件检查，则不允许用半导体检查连接芯片。解决方案：半导体器件1包括：封装基板2; 安装在封装基板2上的半导体芯片3; 形成在封装基板2的第一主面上的第一焊盘210; 形成在封装基板2的第二主表面上的第二焊盘211; 连接到第二焊盘211并且与其连接的第一连接端子213不允许用半导体芯片3检查; 用于连接第一焊盘210和第二焊盘211的连接互连212; 形成在封装基板2的第二主表面上的第二连接端子222; 以及用于连接连接互连212和第二连接端子222的分支互连221.版权所有（C）2010，JPO＆INPIT

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