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131. 发明专利

JPS6155750A Alarm processing of computer system 失效
标题翻译：计算机系统报警处理
公开(公告)号：JPS6155750A
公开(公告)日：1986-03-20
申请号：JP17866584
申请日：1984-08-28
申请人： Fujitsu Ltd
发明人： NOSAKA TAIJI
IPC分类号： G06F11/30 , G06F11/07
CPC分类号： G06F11/0703
摘要： PURPOSE:To handle automatically a system-down without a human touch as much as possible by providing an alarm processing part for issuing the alarm in accordance with the type of the alarm and the operating state of a system. CONSTITUTION:A processor 50 of a power source control part 5 monitors alarms from interfaces 52 and 53, and grasps the operating state of a computer system 1 when the alarm interruption occurs. Since a trouble is considered due to an abnormal power source system when the alarm occurs at the time of turning on a power source, a fan system of a power source unit 3 is checked to be normal or not. After the system is abnormal to investigate a flag in a memory 51, the unit 3 is turned off through the interface 52 to activate an alternative power source unit 4. When the alarm does not occur at the time of turning on a power source, the action state from a service processor 2 is received and the operation is judged to be under the automatic running. Then, since an operator does not exist, a power source is turned off with respect to the abnormality except a main frame after the JOB termination.
摘要翻译：目的：通过提供根据报警类型和系统运行状态发出报警的报警处理部分，尽可能多地自动处理无需人为触摸的系统关闭。构成：电源控制部5的处理器50监视来自接口52,53的报警，并且在发生报警中断时掌握计算机系统1的运行状态。由于当在接通电源时发生报警时由于异常电源系统而考虑到故障，所以检查电源单元3的风扇系统是否正常。在系统异常以检查存储器51中的标志之后，通过接口52关闭单元3以激活替代电源单元4.当打开电源时不发生报警时，接收到来自服务处理器2的动作状态，并且判断该操作处于自动运行状态。然后，由于操作者不存在，所以在作业终止之后，关于除了主框架之外的异常而关闭电源。

132. 发明专利

JPS6140644A Data processing system 失效
标题翻译：数据处理系统
公开(公告)号：JPS6140644A
公开(公告)日：1986-02-26
申请号：JP16213284
申请日：1984-07-31
申请人： Nec Corp
发明人： MAEKAWA KAZUHIKO
IPC分类号： G06F11/00 , G06F1/30 , G06F9/46 , G06F11/07 , G06F15/16
CPC分类号： G06F11/0724 , G06F11/0703
摘要： PURPOSE:To continue processing even if the trouble that the power source of a processor is turned off occurs, by providing a data processing system with an execution display means, an execution process display means, a shared resource update display means, a power break abnormality detecting means, and a control means. CONSTITUTION:If the abbormality of power break occurs in a data processor 30, this state is reported to a diagnostic controller 4. The execution display means of the processor 30 is tested, and contents of a corresponding execution process display means are read out if the execution state is detected. If the readout process is a critical process, the control is set to the abnormal stop state. If it is not a critical process, all lock byte contents are checked; and if there is one or more locks which the processor 30 acquires, the processor 30 is judged to be updating shared resources, and the system is set to the abnormal stop state. If there are no locks, the process is set to the abnormal interrupted state and the data processing is executed continuously by other data processors 31-33 if the resource update display means does not indicate updating.
摘要翻译：目的：为了继续处理，即使处理器的电源出现故障，通过向数据处理系统提供执行显示装置，执行处理显示装置，共享资源更新显示装置，电源中断异常检测装置和控制装置。构成：如果在数据处理器30中发生功率中断的发生，则将该状态报告给诊断控制器4.对处理器30的执行显示单元进行测试，并且读出相应的执行处理显示单元的内容，如果检测到执行状态。如果读出过程是关键过程，则将控制设置为异常停止状态。如果不是关键过程，则检查所有锁定字节内容; 并且如果存在处理器30获取的一个或多个锁，则判断处理器30正在更新共享资源，并且将系统设置为异常停止状态。如果没有锁，则如果资源更新显示装置没有指示更新，则该处理被设置为异常中断状态，并且数据处理由其他数据处理器31-33连续执行。

133. 发明专利

JPS6120147A Displaying system of system status 失效
标题翻译：系统状态显示系统
公开(公告)号：JPS6120147A
公开(公告)日：1986-01-28
申请号：JP13914084
申请日：1984-07-06
申请人： Fujitsu Ltd , Nec Corp , Nippon Telegr & Teleph Corp
发明人： SAKATA HIRONOBU , OKADA KATSUYUKI , SHIMIZU RIYOUICHI
IPC分类号： G06F11/30 , G06F11/07 , H04M3/08 , H04Q1/22
CPC分类号： G06F11/0748 , G06F11/0703
摘要： PURPOSE:To make it possible to collect the status of a system at the detection of the abnormality of a central controller by informing the detection of the abnormality of another processor and holding the system status at the detection so as to be read out. CONSTITUTION:The central controller 1 is connected to an emergency control circuit 2 through an operational abnormality detecting signal 4, a stop request signal 5 and a rise request signal 8, the circuit 2 is connected to a maintenance control device 3 through an operational abnormality informing signal 6 and the devices 1, 3 are connected through a system status reading bus 7. When the device 1 detects abnormality, the signal 4 starts the circuit 2 and the circuit 2 makes the circuit 1 hold at its system status by the signal 5 and commands the device 3 to read out said system status through a signal 6. The device 3 reads out the system status of the device 1 through a bus 7, and during the reading, the circuit 2 is held at timing waiting status. After completing the reading, the device 1 is raised by the signal 8.
摘要翻译：目的：通过通知检测到另一个处理器的异常并保持检测到的系统状态以便读出，可以在检测到中央控制器的异常时收集系统的状态。构成：中央控制器1通过操作异常检测信号4，停止请求信号5和上升请求信号8与应急控制电路2连接，电路2通过操作异常通知连接到维护控制装置3 信号6和设备1,3通过系统状态读取总线7连接。当设备1检测到异常时，信号4启动电路2，电路2通过信号5使电路1保持其系统状态，命令设备3通过信号6读出所述系统状态。设备3通过总线7读出设备1的系统状态，并且在读取期间，电路2保持在定时等待状态。在完成阅读之后，装置1由信号8升高。

134. 发明专利

JPS60209849A Picture forming device 失效
标题翻译：图像形成装置
公开(公告)号：JPS60209849A
公开(公告)日：1985-10-22
申请号：JP6649884
申请日：1984-04-03
申请人： Konishiroku Photo Ind Co Ltd
发明人： FUNABASHI SOUKICHI
IPC分类号： G03G21/00 , G03G21/14 , G05B23/02 , G06F11/00 , G06F11/07
CPC分类号： G06F11/0721 , G06F11/00 , G06F11/0703 , G06F11/0757
摘要： PURPOSE:To clear up causes of program runaway by holding the operation mode just before the occurrence of program runaway. CONSTITUTION:A CPU1 continues to transmit runaway detection clear pulses to a runaway detecting circuit 6 in the normal state. If these clear pulses are broken, runaway of the CPU1 is detected, and a reset signal is transmitted immediately to the CPU1, and a runaway detection signal is outputted for a certain period after transmission of this reset signal. The latest mode is always set and held in an operation mode holding circuit 8. When the CPU1 is reset, an initial routine is executed; and if the runaway detection signal is outputted then, the operation mode just before runaway is written in an area for runaway storage from the holding circuit 8. Meanwhile, the runaway detecting circuit 6 clears the runaway detection signal when several detection clear pulses are inputted thereafter.
摘要翻译：目的：通过在程序失控发生前握住操作模式来清除程序失控的原因。构成：在正常状态下，CPU1继续将失控检测清除脉冲发送到失控检测电路6。如果这些清除脉冲被破坏，则检测到CPU1的失控，并且将复位信号立即发送到CPU1，并且在发送该复位信号之后的某个时间段内输出失控检测信号。最后的模式始终被设置并保持在操作模式保持电路8中。当CPU1复位时，执行初始程序; 并且如果输出失控检测信号，则在失控之前的操作模式被写入到从保持电路8逃逸存储的区域中。同时，失控检测电路6在其后输入若干检测清除脉冲时清除失控检测信号。

135. 发明专利

JPS60193055A Processing system for processor fault 失效
标题翻译：处理器故障处理系统
公开(公告)号：JPS60193055A
公开(公告)日：1985-10-01
申请号：JP4976184
申请日：1984-03-15
申请人： Fujitsu Ltd
发明人： HAYASHI HIDENORI
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G06F11/0703 , G06F11/073
摘要： PURPOSE:To attain the quick recovery or relief for a processor fault by executing forcibly a fault processing program by a CPU when the CPU gives an access to an unpacked space of a memory. CONSTITUTION:A time circuit 3 is provided in addition to a fault processing program data transmission circuit 4, and a CPU1 gives accesses to main memories 2-1 and 2-2. Then the programs are sent successively and forcibly to the CPU1 from the circuit 4 to relieve the fault processing for execution of the prescribed processing in case it is detected from collation with the prescribed time of the circuit 3 that no transfer end signal is sent to the CPU1 from memories 2-1 and 2-2 even after a prescribed period of time elapses.
摘要翻译：目的：通过在CPU对存储器的未打包空间进行访问时，由CPU强制执行故障处理程序，以达到处理器故障的快速恢复或缓解。构成：除了故障处理程序数据发送电路4之外，还设置有时间电路3，CPU1对主存储器2-1,2-2进行存取。然后将程序从电路4连续强制发送到CPU1，以便在与电路3的规定时间对照检测到的情况下解除用于执行规定处理的故障处理，没有传送结束信号被发送到来自存储器2-1和2-2的CPU1即使在经过规定的时间段之后也是如此。

136. 发明专利

JPS60193052A Confirmation system for fault processing function of information processor 失效
标题翻译：信息处理器故障处理功能确认系统
公开(公告)号：JPS60193052A
公开(公告)日：1985-10-01
申请号：JP4719184
申请日：1984-03-14
申请人： Nec Corp
发明人： JITSUPOU AKIRA
IPC分类号： G06F11/00 , G06F11/07 , G06F11/26
CPC分类号： G06F11/0721 , G06F11/0703 , G06F11/261
摘要： PURPOSE:To simplify automatic fault processing operation and to facilitate easy confirmation of fault processing function, by producing a pseudo machine error at a time point designated previously within a program. CONSTITUTION:A program instruction given from a main memory 1 is decoded and executed by an arithmetic control circuit 2. A control register 3 receives a control register set signal from the circuit 2 and controls the generation of a machine error. Then a machine error generation control circuit 8 produces a report on said machine error when an overflow detection signal is supplied while the control register output signal given from the register 3 is kept effective. A fault processor 9 performs the error processing in response to the machine error report signal given from the circuit 8.
摘要翻译：目的：简化自动故障处理操作，简化故障处理功能的确认，通过在程序之前指定的时间点产生伪机错误。构成：由主存储器1给出的程序指令由算术控制电路2解码并执行。控制寄存器3从电路2接收控制寄存器设置信号并控制机器错误的产生。然后，当从寄存器3给出的控制寄存器输出信号保持有效时，机器错误产生控制电路8产生关于所述机器错误的报告，当提供溢出检测信号时。故障处理器9响应于从电路8给出的机器错误报告信号执行错误处理。

137. 发明专利

JPS60189545A Logical device 失效
标题翻译：逻辑设备
公开(公告)号：JPS60189545A
公开(公告)日：1985-09-27
申请号：JP4520384
申请日：1984-03-09
申请人： Toshiba Corp
发明人： KAWAMURA MASAHIKO
IPC分类号： G06F11/22 , G06F11/07 , H03K19/00
CPC分类号： G06F11/0721 , G06F11/0703
摘要： PURPOSE:To specify the position of a failure easily by forming a test-only memory for temporarily storing the contents of an internal bus on the basis of a control signal. CONSTITUTION:A logical device having internal bus structure is provided with a test-only register 5 having the same bit width as an internal data bus 1 and enabled to store a signal on the data bus through a write control terminal 6. A signal for switching an internal microinstruction is supplied to the wirte control terminal 6, and because the register 5 has also a control terminal 7 and an output terminal 8, its contents are fetched to the external when necessary. Since the test-only memory for temporarily storing the information of the internal data bus where a main signal is passed through is buit in the logical device, the troubleshooting of a CPU is made easy.
摘要翻译：目的：通过形成用于根据控制信号临时存储内部总线的内容的仅测试存储器来容易地指定故障的位置。构成：具有内部总线结构的逻辑设备具有与内部数据总线1具有相同位宽的测试寄存器5，并且能够通过写入控制端子6在数据总线上存储信号。用于切换的信号内部微指令被提供给布线控制端子6，并且由于寄存器5还具有控制端子7和输出端子8，所以在必要时其内容被提取到外部。由于用于临时存储主信号通过的内部数据总线的信息的仅测试存储器是逻辑设备中的，所以CPU的故障排除变得容易。

138. 发明专利

JPS59207492A Fault information transfer system of memory control circuit 失效
标题翻译：存储器控制电路故障信息传输系统
公开(公告)号：JPS59207492A
公开(公告)日：1984-11-24
申请号：JP8084083
申请日：1983-05-11
申请人： Hitachi Ltd
发明人： NAKAMURA KOUJI , OKABE TOSHIHIRO , MIMURA KAZUNOBU , FUNAKUBO NOBUO
IPC分类号： G06F12/16 , G06F11/07 , G06F11/30
CPC分类号： G06F11/073 , G06F11/0703
摘要： PURPOSE:To obtain a large quantity of fault information without increasing the number of interface signal lines by using a data line between a memory control circuit and an access device for memory to transfer various types of information when a fault arises. CONSTITUTION:The priority is given from a memory control circuit 2 to the access requests given from plural CPU3 to a memory 1. A signal line 7 is used to report the detection of a fault to a requester in case a fault is detected within the circuit 2 while the access request ie executed after the operation of the circuit 2 is through. In this case, the data of an address rgister 21, a write data register 22 and a read data register 23 are checked by a fault detecting circuit 25. Then the register 23 and a fault information register 24 are selected when no fault is detected and a fault is detected respectively by the selection signal given from the circuit 25.
摘要翻译：目的：通过使用存储器控制电路和存储器访问设备之间的数据线，在故障发生时传送各种类型的信息，而不增加接口信号线的数量来获得大量的故障信息。构成：从存储器控制电路2给出从多个CPU3向存储器1提供的访问请求的优先权。信号线7用于在电路内检测到故障的情况下向请求者报告故障的检测 2，而在电路2的操作之后执行的访问请求是通过的。在这种情况下，由故障检测电路25检查地址寄存器21，写数据寄存器22和读数据寄存器23的数据。然后，当没有检测到故障时，选择寄存器23和故障信息寄存器24，通过从电路25给出的选择信号分别检测故障。

139. 发明专利

JPS59172049A Error data recording system 失效
标题翻译：错误数据记录系统
公开(公告)号：JPS59172049A
公开(公告)日：1984-09-28
申请号：JP4737083
申请日：1983-03-22
申请人： Fujitsu Ltd
发明人： SAITOU KIYOSHI
IPC分类号： G06F11/34 , G06F11/07
CPC分类号： G06F11/073 , G06F11/0703
摘要： PURPOSE:To facilitate search of the cause of a trouble for the occurrence of an error by recording date data of the time, when the error occurs, together with a device number and error information. CONSTITUTION:When an error occurs in an OCR4, error information E4 is sent to a control part 6. The control part 6 reports error information E4 and a device number N4 to a processing part 9. The processing part 9 starts a logging program P in a main memory 10 to starts its execution. Then, the device number N4 is written in a column (n) of the fourth item C4 of a logger area 12 in a memory 11, and error information E4 is written in a column (e), and date data (3, 1, 16, 40) of the error occurrence time due to a time counter 7 is written in a column (d). This date data indicated that the error occurs on the first of March at 40min past sixteen. The same operation is performed for the occurrence of errors in other devices. Logging data in the memory 11 is compared and collated with journal information to facilitate searching causes of troubles.
摘要翻译：目的：通过记录时间的日期数据，发生错误以及设备编号和错误信息，便于查找出现故障的原因。构成：当OCR4发生错误时，将错误信息E4发送给控制部6.控制部6向处理部9报告错误信息E4和设备号N4。处理部9将记录程序P开始主存储器10开始执行。然后，将设备编号N4写入存储器11中记录器区域12的第四项C4的列（n），并将错误信息E4写入列（e），并将日期数据（3,1，（d）中写入由时间计数器7引起的错误发生时间。这个日期数据表明，错误发生在三月一号，十六分钟以后40分钟。对其他设备中的错误的发生执行相同的操作。将存储器11中的记录数据与日志信息进行比较和整理，以便于搜索故障的原因。

140. 发明专利

JPS59146354A Runaway stopping device of microprocessor 失效
标题翻译：微处理器RUNAWAY停止装置
公开(公告)号：JPS59146354A
公开(公告)日：1984-08-22
申请号：JP1999083
申请日：1983-02-09
申请人： Matsushita Electric Ind Co Ltd
发明人： SATOU HIDETO
IPC分类号： G06F11/30 , G06F11/00 , G06F11/07
CPC分类号： G06F11/0757 , G06F11/0703 , G06F11/0721
摘要： PURPOSE:To stop automatically operation of a microprocessor and its peripheral circuit by providing a watchdog timer (monitor timer) function and etc. and detecting runaway to hold them in a reset state. CONSTITUTION:A microprocessor 1 incorporates the watchdog timer function besides a normal function. When the processor 1 runs away, an output (b) is not outputted, and consequently, a counter 4 is not reset; and if this state continued for, for example, 13 seconds, a circuit 4 is changed from a low level to a high level. Then, the input T of the second FF6 is set, and a reset pulse is inputted to the reset terminal (d) of the processor 1 through a gate 8 together with the output of a reset pulse generating circuit 3 to stop the operation automatically. The monitor timer function is provided to detect runaway in this manner, thus stopping the microprocessor or the like automatically.
摘要翻译：目的：通过提供看门狗定时器（监视定时器）功能等来防止微处理器及其外围电路的自动运行，并检测失控，使其保持在复位状态。构成：除正常功能外，微处理器1还集成了看门狗定时器功能。当处理器1消失时，输出（b）不输出，因此计数器4不被复位; 并且如果该状态持续例如13秒，则电路4从低电平变为高电平。然后，设置第二FF6的输入端T，并且通过门8与复位脉冲发生电路3的输出一起将复位脉冲输入到处理器1的复位端（d），以自动停止操作。提供监视定时器功能以以这种方式检测失控，从而自动停止微处理器等。

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