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101. 发明专利

JPS5960527A Input and output port 失效
标题翻译：输入和输出端口
公开(公告)号：JPS5960527A
公开(公告)日：1984-04-06
申请号：JP17030682
申请日：1982-09-29
申请人： Toshiba Corp
发明人： SATOU IKUO
IPC分类号： G06F3/00 , G06F11/07 , G06F13/40
CPC分类号： G06F11/0745 , G06F11/0703 , G06F13/4068
摘要： PURPOSE:To execute effectively maintenance by interrupting quickly connection with a bus line at the time of abnormality of a power source, by a photoelectric coupler connected to a power source line, in an input/output port connected to the power source line. CONSTITUTION:When a power source VDD is normal, LEDs 36, 38 and 40 emit light, phototransistors TR32, 30 and 34 become a conductive state, and data can be sent and received between a bus line 12 and an I/O port 14. On the contrary, if a fuse 20 is fused due to a short circuit of the power source VDD, etc., the LEDs 36, 38 and 40 do not emit light, therefore, the TRs 32, 30 and 34 become a nonconductive state. As a result, tri-state buffers 16, 18 are cut off electrically from the bus line. As a result, the I/O port can be replaced in a state that the power source line is in electic conduction.
摘要翻译：目的：通过连接到电源线的光电耦合器连接到电源线的输入/输出端口，通过中断与电源异常时的总线快速连接来有效地执行维护。构成：当电源VDD正常时，LED 36,38和40发光，光电晶体管TR32,30和34变为导通状态，数据可以在总线12和I / O端口14之间发送和接收。相反，如果熔断器20由于电源VDD等的短路而熔断，则LED36,38和40不发光，因此TR32,32和34变为非导通状态。结果，三态缓冲器16,18与总线电断开。结果，可以在电源线处于导通状态的状态下更换I / O端口。

102. 发明专利

JPS5953941A Information processing device 失效
标题翻译：信息处理设备
公开(公告)号：JPS5953941A
公开(公告)日：1984-03-28
申请号：JP16447682
申请日：1982-09-21
申请人： Nec Corp
发明人： JITSUPOU AKIRA
IPC分类号： G06F11/10 , G06F9/22 , G06F11/07 , G06F12/16
CPC分类号： G06F11/0721 , G06F11/0703
摘要： PURPOSE:To minimize te influence exerted on performance, and to raise reliability and a maintenance property of a device, by providing a means for inhibiting or releasing the generation of an error report signal, and discriminating whether a correctable error is a fixed fault or a temporary fault. CONSTITUTION:In case when a correctable error is detected by an error detecting and correcting circuit 2, ''1'' is added to contents of an error generation frequency storing circuit 5 by a detecting signal 34 for reporting said detection. Subsequently, a value 36 of correctable error generation frequency of the circuit 5 is compared with an initial set value 38 of an error threshold circuit 6 by a comparing circuit 7. When they coincide with each other, an error report is inhibited by an error report controlling circuit 9. Subsequently, a time monitoring signal 41 is outputted to a time monitoring circuit 8 from the circuit 9, its initial set value 43 is subtracted by ''1'' each in accordance with the signal 41, and when its value is reduced to ''0'', a monitoring end signal 40 is generated and is inputted to the circuit 9. The circuit 9 refers to the value 36, and releases the inhibition of the error report if a value of correctable error generation frequency in the course of the time monitoring is ''0''.
摘要翻译：目的：为了减少对性能的影响，提高设备的可靠性和维护性能，通过提供一种抑制或解除生成错误报告信号的方法，以及判断一个可纠正的错误是固定故障还是临时性错误。构成：如果由错误检测和校正电路2检测到可纠正的错误，则通过用于报告所述检测的检测信号34将“1”添加到错误产生频率存储电路5的内容。随后，通过比较电路7将电路5的可校正错误产生频率的值36与误差阈值电路6的初始设定值38进行比较。当它们相互重合时，错误报告被错误报告随后，时间监视信号41从电路9输出到时间监控电路8，其初始设定值43根据信号41相减“1”，当其值为减少为“0”，产生监视结束信号40并将其输入到电路9.电路9参照值36，并且如果在可能的错误产生频率中的值为时间监控的过程是“0”。

103. 发明专利

JPS5935252A Data output circuit 失效
标题翻译：数据输出电路
公开(公告)号：JPS5935252A
公开(公告)日：1984-02-25
申请号：JP14463882
申请日：1982-08-23
申请人： Hitachi Eng Co Ltd , Hitachi Ltd
发明人： MATSUURA SHIYUNZOU
IPC分类号： G06F11/30 , G06F11/07
CPC分类号： G06F11/073 , G06F11/0703
摘要： PURPOSE:To output only normal data, by providing a circuit which locks the output when a program is abnormal or in a runaway state, to the data output circuit of a device which monitors the program by using a microcomputer. CONSTITUTION:A control command (a) passed through a data reception part 1 is code-converted by a code conversion part 2 and operation data J is stored in an operation data memory part 4 by an operation data write trigger (e). At the same time, a one-shot circuit 8 for an operation output enable trigger lock signal is activated by the operation data write trigger (e) to set an operation data output enable data block time. When a software abnormality detection part 10 detects program abnormality or a runaway, selection data and operation data in a selection data memory part 3 and an operation data memory part 4 are cleared. Consequently, even when an operation data output enable trigger (i) is outputted, no abnormal operation data is outputted.
摘要翻译：目的：通过在程序异常或失控状态下提供将输出锁定的电路输出到仅使用正常数据的电路，通过使用微型计算机监视程序的设备的数据输出电路。构成：通过数据接收部分1的控制命令（a）由代码转换部分2进行代码转换，操作数据J通过操作数据写入触发（e）存储在操作数据存储器部分4中。同时，通过操作数据写入触发（e）激活用于操作输出使能触发锁定信号的单触发电路8，以设置操作数据输出使能数据块时间。当软件异常检测部分10检测到程序异常或失控时，清除选择数据存储器部分3和操作数据存储器部分4中的选择数据和操作数据。因此，即使当输出操作数据输出使能触发（i）时，也不输出异常运算数据。

104. 发明专利

JPS5935251A Registration and information system for error of data processor 失效
标题翻译：数据处理器错误的注册和信息系统
公开(公告)号：JPS5935251A
公开(公告)日：1984-02-25
申请号：JP14432182
申请日：1982-08-20
申请人： Nec Corp
发明人： OOTAKE AKITO
IPC分类号： G06F11/34 , G06F11/07
CPC分类号： G06F11/0721 , G06F11/0703
摘要： PURPOSE:To prevent the loss of detail information, by providing a command for permitting the registration of a detected error and a command for inhibiting the registration. CONSTITUTION:A detail information storage register 23 is stored with the identification code 202 of an error from an error detecting circuit 24 and address information outputted from an address register 22. In memory scanning operation, even if an error is detected in a command 101 from a central processor 1, its details are not registered in the register 23. In normal read/write operation, a command for setting the output 203 of a command register 21 to ''0'' is sent out to register the details of the error in the register 23.
摘要翻译：目的：为了防止丢失详细信息，通过提供允许检测到的错误的注册命令和禁止注册的命令。构成：细节信息存储寄存器23存储有来自错误检测电路24的错误的识别码202和从地址寄存器22输出的地址信息。在存储器扫描操作中，即使在命令101中检测到错误，中央处理器1，其细节未登记在寄存器23中。在正常读/写操作中，发送用于将命令寄存器21的输出203设置为“0”的命令，以注册错误的细节在登记册23。

105. 发明专利

JPS595305A Data collecting method 失效
标题翻译：数据收集方法
公开(公告)号：JPS595305A
公开(公告)日：1984-01-12
申请号：JP11526782
申请日：1982-07-02
申请人： Meidensha Electric Mfg Co Ltd
发明人： UCHIUMI HIROAKI
IPC分类号： G05B9/02 , G06F11/07 , G06F11/14 , G06F17/40 , H02P27/06
CPC分类号： G06F11/0745 , G06F11/0703
摘要： PURPOSE:To prevent a malfunction and an erroneous display, by performing a countermeasure for a noise, by a software, in case of collecting a data of a microcomputer. CONSTITUTION:DC electric power from a converter 1 is converted to AC power by an invertor 2, is supplied to a synchronous motor 3, and a load 4 of the motor 3 is controlled to a set speed. A microcomputer 5 applies a gate control signal to the invertor 2 and the converter 1, and executes a short-circuit current detection by detecting a current of a smoothing capacitor 6, and a load short- circuit detection by detecting a load current, in order to protect a device or in order to protect a load. Also, the microcomputer executes a propriety deciding processing by a software for a data collection from an operation panel 7 or an abnormality detecting data collection from a main circuit, and executes a collection of a correct data corresponding to a variation of a control state.
摘要翻译：目的：为了防止故障和错误的显示，通过执行对噪声的对策，通过软件，在收集微型计算机的数据的情况下。构成：通过逆变器2将来自转换器1的直流电力转换为交流电力，被提供给同步电动机3，电动机3的负载4被控制到设定速度。微型计算机5向反相器2和转换器1施加栅极控制信号，并通过检测平滑电容器6的电流来执行短路电流检测，并按顺序检测负载电流进行负载短路检测以保护设备或为了保护负载。此外，微型计算机通过来自操作面板7的数据收集软件或从主电路进行的异常检测数据采集来执行适当决定处理，并执行与控制状态的变化对应的正确数据的收集。

106. 发明专利

JPS58223828A Control adaptor switching system of input and output subsystem 失效
标题翻译：输入和输出子系统的控制适配器切换系统
公开(公告)号：JPS58223828A
公开(公告)日：1983-12-26
申请号：JP10803082
申请日：1982-06-23
申请人： Fujitsu Ltd
发明人： NAGASAKA MOTOYUKI
IPC分类号： G06F13/14 , G06F11/07 , G06F11/20 , G06F13/00
CPC分类号： G06F11/0745 , G06F11/0703
摘要： PURPOSE:To reduce the load of a high-order device and to improve the efficiency of an information processing system, by using a substitute control adaptor to accept actuation although the control adaptor of one side has a fault. CONSTITUTION:A selecting circuit 25 for control adaptor A selects a control adaptor A3 and a driver 5 through a low-order interface circuit 24. If the adaptor A3 has a fault, the actuation of the device 5 has an abnormal completion. When an error detecting circuit 23 detects the abnormal completion, the circuit 23 reports the abnormal completion to an upper device 1 from a high-order interface circuit 21 and through an error reporting circuit 22. At the same time, the circuit 23 actuates an adaptor switch circuit 27. Then a selecting circuit 26 for control adaptor B selects a control adaptor B4 and the driver 5 through the circuit 24.
摘要翻译：目的：为了减少高阶设备的负载并提高信息处理系统的效率，尽管一侧的控制适配器有故障，但通过使用替代控制适配器来接受启动。构成：用于控制适配器A的选择电路25通过低阶接口电路24选择控制适配器A3和驱动器5.如果适配器A3有故障，则设备5的致动异常完成。当错误检测电路23检测到异常完成时，电路23从高阶接口电路21和错误报告电路22向上位装置1报告异常完成。同时，电路23致动适配器开关电路27.然后，控制适配器B的选择电路26通过电路24选择控制适配器B4和驱动器5。

107. 发明专利

JPS58201156A Trouble processing system 失效
标题翻译：故障处理系统
公开(公告)号：JPS58201156A
公开(公告)日：1983-11-22
申请号：JP8553782
申请日：1982-05-20
申请人： Fujitsu Ltd
发明人： OGINOYA YUTAKA
IPC分类号： G06F11/34 , G06F11/07
CPC分类号： G06F11/0745 , G06F11/0703
摘要： PURPOSE:To speed up trouble processing of each peripheral device and to maintain each device as a single body, by providing each peripheral device with a means which collects necessary trouble information, and edits and displays it when the trouble happened to the peripheral device. CONSTITUTION:When a check circuit detects trouble of an input/output device 3 or input/output controller 2, an input/output control mechanism 4 generates sense data by referring to operation environ information, etc. The data is stored in a buffer 5 and a timer calendar mechanism 7 reads data and time data on the trouble from a cpul. Then, the data and time data, physical number of the troubled device, and sense data are printed out on a printer 6 in hexadecimal notation (or decimal notation) and the contents of the buffer 5 are cleared.
摘要翻译：目的：为了加快每个外围设备的故障处理并将每个设备保持为一体，通过为每个外围设备提供收集必要的故障信息的方法，并在外围设备发生故障时进行编辑和显示。构成：当检查电路检测到输入/输出设备3或输入/输出控制器2的故障时，输入/输出控制机构4通过参考操作环境信息等产生感测数据。数据被存储在缓冲器5和定时器日历机构7从CPU读取关于故障的数据和时间数据。然后，数据和时间数据，故障设备的物理号和感测数据以十六进制符号（或十进制）表示在打印机6上，缓冲器5的内容被清除。

108. 发明专利

JPS58192123A Device for transferring and controlling input and output data 失效
标题翻译：用于传输和控制输入和输出数据的设备
公开(公告)号：JPS58192123A
公开(公告)日：1983-11-09
申请号：JP7470482
申请日：1982-05-04
申请人： Mitsubishi Electric Corp
发明人： FUJITA MITSUAKI
IPC分类号： G06F13/12 , G06F11/07
CPC分类号： G06F11/0745 , G06F11/0703
摘要： PURPOSE:To reduce the required time for transfer at error generation, by saving a head address from an address register to an address save register and saving the content of a count register at that time to a count save register. CONSTITUTION:An input and output device 5 outputs a save latch signal, every time the transfer of four data is finished from the transfer start point. When the device prepares for data and it is detected that the data block has an error, a list request signal is outputted from the device 5 in place of the data. A channel controlling section 301 receiving this signal outputs a switching signal and a count latch signal, and the content of an address save register 317 and a count save register 318 is latched to an address register 302 and a count register 303. The content of the registers 302, 303 represents the head data of the data block where the error is detected, then the transfer is retried from the state.
摘要翻译：目的：通过将地址寄存器中的头地址保存到地址保存寄存器，并将此时的计数寄存器的内容保存到计数保存寄存器，减少错误生成时所需的传输时间。构成：输入输出装置5输出保存锁存信号，每次从传送开始点传送四个数据。当设备准备数据并且检测到数据块具有错误时，从设备5输出列表请求信号来代替数据。接收该信号的信道控制部分301输出切换信号和计数锁存信号，地址存储寄存器317和计数保存寄存器318的内容被锁存到地址寄存器302和计数寄存器303。寄存器302,303表示检测到错误的数据块的头数据，然后从该状态重试传送。

109. 发明专利

JPS58189748A Storage device of state information 失效
标题翻译：国家信息存储设备
公开(公告)号：JPS58189748A
公开(公告)日：1983-11-05
申请号：JP7218682
申请日：1982-04-28
申请人： Mitsubishi Electric Corp
发明人： KODAMA TAKASHI
IPC分类号： G06F11/34 , G06F11/07
CPC分类号： G06F11/073 , G06F11/0703
摘要： PURPOSE:To perform debugging with high efficiency for a state information storage device of an electronic computer, by recording the state of information on the kind and the generation time of an error. CONSTITUTION:When a signel logic in an error generating signal group 9 is set at 1, a write enable signal 7 is delivered by the next clock signal 5. Then the state information 2 is written to a stack 1, and at the same time the contents of the group 9 are written at other position of the same address. The logic of an error generating signal 6 is set at 1 after the contents of the group 9 are written to the stack 1. This prevents the output of the signal 7 and inhibits the working of an address forming circuit 4. Therefore it is possible to understand the progress of generation of an error and the kind and the generating time of the error by checking the record of the stack 1.
摘要翻译：目的：通过记录关于错误的种类和生成时间的信息状态，高效地进行电子计算机的状态信息存储装置的调试。构成：当错误产生信号组9中的信号逻辑被设置为1时，写入使能信号7由下一个时钟信号5传送。然后将状态信息2写入堆栈1，同时将组9的内容被写入同一地址的其他位置。在将组9的内容写入堆栈1之后，将误差产生信号6的逻辑设置为1，这样可以防止信号7的输出并阻止地址形成电路4的工作。因此，通过检查堆栈1的记录，了解错误生成的进度和错误的种类和生成时间。

110. 发明专利

JPS58182761A Data checking system 失效
标题翻译：数据检查系统
公开(公告)号：JPS58182761A
公开(公告)日：1983-10-25
申请号：JP6594982
申请日：1982-04-20
申请人： Fujitsu Ltd
发明人： SUZUKI OSAMU
IPC分类号： G06F11/30 , G06F11/00 , G06F11/07
CPC分类号： G06F11/073 , G06F11/0703
摘要： PURPOSE:To obtain an economical device and at the same time to ensure the fine recovery, by reporting the error information after discriminating the information in response to the purpose of application of a memory in case a data error arises at the memory. CONSTITUTION:A data address is applied to a memory 1 by a multiplexer 6 for writing and reading when the memory 1 is used as a data buffer. A data checking circuit 5 gives a parity check to the data which is read out of the memory 1. In the case of a parity error, an error is reported through a terminal DATACHECK. When the memory 1 is used for a work, the multiplexer 6 gives a work address to the memory 1 to perform the writing or reading of the control data. The control data read out of the memory 1 is set to a memory interface register 2, and the parity is checked by a data checking circuit 4.
摘要翻译：目的：为了获得经济的设备，同时通过在存储器发生数据错误的情况下响应于应用存储器的目的鉴别信息之后报告错误信息，同时确保精确恢复。构成：当存储器1用作数据缓冲器时，由多路复用器6将数据地址应用于存储器1用于写入和读取。数据检查电路5对从存储器1读出的数据给出奇偶校验。在奇偶校验错误的情况下，通过终端DATACHECK报告错误。当存储器1用于工作时，多路复用器6给出存储器1的工作地址以执行控制数据的写入或读取。从存储器1读出的控制数据被设置到存储器接口寄存器2，并且由数据检查电路4检查奇偶校验。

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