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91. 发明专利

JPH09294093A EQUALIZATION CIRCUIT FOR INTRA-STATION LINE TERMINATION PANEL 失效
公开(公告)号：JPH09294093A
公开(公告)日：1997-11-11
申请号：JP10696696
申请日：1996-04-26
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： KOMATSU KAZUTOSHI , KAKINUMA RIYUUMA , YAMANO SEIICHI
IPC分类号： H04B3/08 , H04L7/027
摘要： PROBLEM TO BE SOLVED: To realize the simplified and small-sized equalization circuit for an intra-station line termination panel. SOLUTION: A reception signal whose noise is eliminated is normalized by an AGC(automatic gain control) circuit 31. An adder 32 revises a level of an output signal of the AGC 31 in response to a feedback signal. A phase discrimination means 40 frequencydivides a fixed oscillating frequency to use a plurality of signals ϕ1-ϕ8 whose phases are shifted and to sample an output signal of the adder 32 thereby setting a timing corresponding to a rising of the output signal of the adder 32. A sampling means 60 samples the output signal of the adder 32 synchronously with a set timing to generate reproduction data. On the other hand, a BT equalizer 51 and a transfer 52 generate the feedback signal depending on a code of the reproduction data at that point of time synchronously with the set timing and gives the signal to the adder 32.

93. 发明专利

JPH09261211A BIT SYNCHRONIZATION SYSTEM 失效
公开(公告)号：JPH09261211A
公开(公告)日：1997-10-03
申请号：JP8992896
申请日：1996-03-21
申请人： KOKUSAI ELECTRIC CO LTD
发明人： TOCHIHARA SHUNJI
IPC分类号： H03K5/135 , H03K5/00 , H04L7/027 , H04L25/40
摘要： PROBLEM TO BE SOLVED: To provide a bit synchronization system by recovering an optimum reception clock from reception signal data whose duty ratio is not balanced in its waveform so as to capture bit synchronization regardless of received data for a short time. SOLUTION: In the bit synchronization system provide with a reception section receiving serial data, a clock generating section 3 recovering from the received data its transmission timing, and a signal detection section 4 detecting the received data based on the clock timing, a recovery clock signal is generated in the timing of a median of integration of detected leading timings and of detected trailing timings of the received data.

95. 发明专利

JPH09238168A METHOD AND DEVICE FOR SIGNAL SYNCHRONIZATION FOR SIGNAL RECEPTION STATION 失效
公开(公告)号：JPH09238168A
公开(公告)日：1997-09-09
申请号：JP550397
申请日：1997-01-16
申请人： EUROP AGENCE SPATIALE
发明人： JIYUZETSUPE KAIRE , KARURO ERIA
IPC分类号： H04L27/14 , H04L7/00 , H04L7/027 , H04L27/227
摘要： PROBLEM TO BE SOLVED: To obtain a synchronization means for a non-coherent orthogonal FSK modulation signal capable of performing open loop operation at an operating point with a low S/N by specifying a maximum spectrum peak of a sample signal. SOLUTION: A plurality of sample signals y1 obtained by interleaving a received burst with a different sampling epoch N0 are fed to a high speed Fourier transformation device FFT. The FFT outputs a plurality of version frequency spectrums F(0), F(1),... corresponding to each sampling epoch N0 . A maximum calculation cell MAX specifies a peak of each frequency spectrum and a comparator CP specifies a sample signal y1 having a maximum spectral peak. A MUX cell calculates an estimate value of a frequency offset from the data and gives it to a numeral control oscillator(NCO). The sample signal stored in a RAM buffer is subject to frequency correction by a complex signal tone from the NCO and the result is sent to a non-coherent demodulator.

99. 发明专利

JPH09135239A CLOCK EXTRACTION CIRCUIT 失效
公开(公告)号：JPH09135239A
公开(公告)日：1997-05-20
申请号：JP31730995
申请日：1995-11-10
申请人： TOYO COMMUNICATION EQUIP
发明人： AKEGAMIYAMA YUKIO
IPC分类号： H04L25/49 , H04L7/00 , H04L7/027
摘要： PROBLEM TO BE SOLVED: To obtain the same performance as the use of a phase synchronization oscillator from a small sized device without use of the phase synchronization oscillator by unchanging a phase of a clock signal so long as the count of a counter does not reach a prescribed number even when a code error is in existence in data. SOLUTION: A counter 6a outputs an RC at a proper time and a counter 6b does never output an RC, then a J-K flip-flop 7 and a selection circuit 8 output a signal F1 as a phase of a clock signal f0 . Even when a code error is in existence in data, so long as the count of the counters 6a, 6b does not reach a prescribed number, e.g. N, the phase of the clock signal f0 is unchanged. That is, even when a pulse is given once to a D latch circuit 4b by the signal F1, the counter 6b is cleared by a pulse output of a succeeding D latch circuit 4b. Thus, the clock signal is made stable without use of an expensive phase synchronization oscillator only by externally mounting a simple logic circuit.

100. 发明专利

JPH09102805A CLOCK EXTRACTION CIRCUIT 失效
公开(公告)号：JPH09102805A
公开(公告)日：1997-04-15
申请号：JP27968495
申请日：1995-10-03
申请人： TOYO COMMUNICATION EQUIP
发明人： OGAWA YUKIO , NAKANO SHIGEYOSHI
IPC分类号： G10K15/04 , H04L7/027 , H04L27/14
摘要： PROBLEM TO BE SOLVED: To attain the free setting of communication speed and to facilitate maintenance in an RF MODEM by providing a digital filter extracting a signal with a frequency which is optionally selected to an input data signal and a circuit identifying a clock signal based on the picked-up signal. SOLUTION: The digital filter 5 is provided with adders 6 and 7 adding a signal value which is superimposed on a signal line, delay circuits 8 and 9 and coefficient multipliers 10-14 with a function as a coefficient selecting part. In the digital filter 5, coefficients corresponding to communication speed as the coefficient values of a1-a3, b1 and b2 in the coefficient multipliers 10-14 are respectively selected so that the frequency of a reception clock corresponding to the data transfer speed of a master side RF MODEM and a slave side RF MODEM. Then, in the identifying circuit 4, the amplitude of an output waveform from the digital filter 5 is measured, a pulse is generated when the measured value exceeds a threshold value and the reception clock signal RXC is outputted.

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