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91. 发明专利

JPS60204190A DISPLAY CIRCUIT 失效
公开(公告)号：JPS60204190A
公开(公告)日：1985-10-15
申请号：JP6032084
申请日：1984-03-28
申请人： SONY CORP
发明人： MAEDA SATORU , MOTOKI KAZUO , NOGUCHI YASUSHI
IPC分类号： G09G1/06 , G09G5/28 , H04N7/173
摘要： PURPOSE:To apply correct smoothing even at both right/left ends of a page by writing in advance a dummy where bits adjacent to the start and end bits of a horizontal display period are logical ''0'' to an address not used for the display of a display memory. CONSTITUTION:A horizontal address signal HADR from a presettable counter 5 is changed at each unit period tau corresponding to one address of the display memory 1 and the signal HADR is fed to the memory 1 so as to read the display data. Then the signal HADR is taken as address [0]-[3] not used for the display in the memory 1, read from the memory 1 and subject to processing of logical ''0''. Then the dummy data where bits adjacent to bits of the start and end of the horizontal display period are logical ''0'' is written in advance to the addresses [0]-[3]. Thus, the smoothing is attained correctly at both right/left ends of a page.

92. 发明专利

JPS60173576A PULSE FORMATION CIRCUIT 失效
公开(公告)号：JPS60173576A
公开(公告)日：1985-09-06
申请号：JP2557384
申请日：1984-02-14
申请人： NIPPON TELEGRAPH & TELEPHONE , SONY CORP
发明人： SHIBUI MICHIROU , UENISHI TOSHIFUMI , MAEDA SATORU
IPC分类号： H04N7/08 , G09G1/00 , G09G5/28 , H04N7/025 , H04N7/03 , H04N7/035 , H04N7/081 , H04N7/16 , H04N7/173

93. 发明专利

JPS6078478A CHARACTER DISPLAY 失效
公开(公告)号：JPS6078478A
公开(公告)日：1985-05-04
申请号：JP18563183
申请日：1983-10-04
申请人： NIPPON TELEGRAPH & TELEPHONE , SONY CORP
发明人： KATAGIRI KOUICHI , SUDOU TAKASHI , MAEDA SATORU
IPC分类号： G09G5/24 , G09G1/00

94. 发明专利

JPS6061791A DISPLAY CIRCUIT 失效
公开(公告)号：JPS6061791A
公开(公告)日：1985-04-09
申请号：JP17047583
申请日：1983-09-14
申请人： SONY CORP
发明人： MAEDA SATORU , MOTOKI KAZUO , NOGUCHI YASUSHI
IPC分类号： G09G5/00 , G09G1/02 , G09G5/14 , G09G5/18

95. 发明专利

JPS6030286A DISPLAY CIRCUIT 失效
公开(公告)号：JPS6030286A
公开(公告)日：1985-02-15
申请号：JP13815783
申请日：1983-07-28
申请人： SONY CORP
发明人： MAEDA SATORU , YOSHIKAWA MUNEHIRO
IPC分类号： H04N7/08 , G09G1/06 , G09G5/00 , G09G5/32 , H04N7/025 , H04N7/03 , H04N7/035 , H04N7/081 , H04N7/083 , H04N7/087 , H04N7/088
摘要： PURPOSE:To increase a drawing speed and simplify circuit constitution by providing a video RAM having capacity corresponding to high-density display, and accessing and displaying display data only in a quarter area of the video RAM in normal display. CONSTITUTION:A flip-flop 35 is set with a command from a CPU in high-density mode, and a clock CK and a pulse HB are supplied from selectors 33 and 34 to horizontal and vertical address generating circuits 37 and 38. Consequently, display data is read out of the video RAM16, byte by byte, synchronizing with a horizontal and a vertical scan and supplied to a register 41 to obtain a luminance signal Y for high-density display. The flip-flop 35 is reset in normal display and pulses HCK and HHD which have frequencies a half as high as the clock CK and pulse HD are supplied to the generating circuits 37 and 38, so data only in a quarter area of the video RAM16 is read out and supplied to the register 41 to obtain a luminance signal Y for normal display.

96. 发明专利

JPS6029072A ERROR CORRECTING DEVICE 失效
公开(公告)号：JPS6029072A
公开(公告)日：1985-02-14
申请号：JP13473883
申请日：1983-07-22
申请人： SONY CORP
发明人： MAEDA SATORU , NOGUCHI YASUSHI
IPC分类号： H03M13/00 , H04N7/025 , H04N7/03 , H04N7/035 , H04N7/08 , H04N7/22 , H04N17/00
摘要： PURPOSE:To improve process speed and to make unnecessary the installation of a multilevel shift register by reading memory data, performing parallel/serial conversion, correcting errors, and then writing memory data again in the memory after making serial/parallel conversion. CONSTITUTION:The input data signals are converted into parallel codes in a serial parallel conversion circuit 1, then latched in a latch circuit 7. The latch data are written in the prescribed addresses in a buffer memory 10. Then the contents of the memory 10 are orderly read, converted into the serial codes in a parallel/serial conversion circuit 14, and loaded in the syndrome register. A B2 bit register 15, a majority circuit 16 and an exclusive logic circuit 18 constitute an error correcting circuit; the data from the circuit are corrected, if any errors are contained, by these circuits 15, 16 and 18, then converted into parallel codes by the circuit 1 through a selector 13, and latched by the circuit 7. The data after corrected the circuit 7 are written in the prescribed addresses in the memory 10.

97. 发明专利

JPS60174A TELEVISION RECEIVER 失效
公开(公告)号：JPS60174A
公开(公告)日：1985-01-05
申请号：JP10820683
申请日：1983-06-16
申请人： SONY CORP
发明人： KATSUBE AKINORI , MAEDA SATORU , NOGUCHI YASUSHI
IPC分类号： H04N5/45
摘要： PURPOSE:To prevent the disturbance of a picture by controlling write/read to/from a display memory based on a synchronizing signal generated from a synchronizing signal generating circuit, and driving picture tube by a video signal read from the display memory. CONSTITUTION:A video signal Svo from a turner 2 is supplied to a switch circuit 3. Further, the signal Svo from the tuner 2 is supplied to a buffer memory 20. This memory 20 has a storage capacity for one division of screen's share when plural channels of picture contents are displayed on a screen. The video signal read from the memory 20 is applied to a display memory 4 having a storage capacity for one screen's share. Further, a video signal Sv1 read from the memory 4 is supplied to the circuit. 3. Then the output of the circuit 3 is supplied to the picture tube 5. Thus, since the fetching of the video signal to the buffer memory and the read from the display memory are conducted completely separately, no disturbance of picture on the display face-plate is caused even if the video signal is changed over.

98. 发明专利

JPS59231984A DISPLAY DEVICE 失效
公开(公告)号：JPS59231984A
公开(公告)日：1984-12-26
申请号：JP10625583
申请日：1983-06-14
申请人： SONY CORP
发明人： MAEDA SATORU , MOTOKI KAZUO , TAKANO SHIYUNSUKE
IPC分类号： H04N7/08 , G09G5/00 , G09G5/36 , H04N7/025 , H04N7/03 , H04N7/035 , H04N7/081
摘要： PURPOSE:To provide advantageous circuit integration to the device by inverting a data on a display memory at input/output, writing logical ''1'' at erasing and generating data by means of resistors only to simplify the circuit. CONSTITUTION:In erasing content of the display memory 4, an erase instruction signal SE is applied from a CPU to erasing period generating circuit 10 and the circuit 10 applies an erasing pulse PE to a control circuit 9. A write signal is applied to the memory 4 from a termianl WE' of the circuit 9 during the period of the pulse PE to attain write state. Further, an address signal DISAD is applied to an address terminal A of the memory 4 from an output terminal Y of an address selector 1. Moreover, an output terminal Y' of a bus drive 5 is brought into the high impedance state during this period. Since each line of the data bus 6 is connected to a power supply +B via a resistor 8, a data of logical ''1'' is written in the memory 4 during this period based on the signal DISAD. Thus, this state is apparently the same as erasure of content of the memory 4.

99. 发明专利

JPS59175285A Forming circuit of synchronizing pulse 失效
标题翻译：形成同步脉冲的电路
公开(公告)号：JPS59175285A
公开(公告)日：1984-10-04
申请号：JP4976983
申请日：1983-03-25
申请人： Sony Corp
发明人： MAEDA SATORU
IPC分类号： H04N5/06
CPC分类号： H04N5/06
摘要： PURPOSE:To simplify the constitution by frequency-dividing an oscillation output of a VCO, forming a horizontal synchronizing pulse from the frequency-divided output and further frequency-dividing it to control the VCO by an output as a result of phase comparison with the standard horizontal synchronizing pulse. CONSTITUTION:A clock for non-interlace display from the VCO 61 is applied to a frequency dividing circuit 62, where the clock is frequency-divided into 2fh (standard value), its output is supplied to a decoder 63 and decoded outputs Pj and Pk are extracted. This output is fed to an FF64 and a horizontal synchronizing pulse is led out. This pulse is applied to a T flip-flop 65 and frequency- divided by 2/1, this pulse is supplied to a phase comparison circuit 66, where the phase of the pulse is compared with that of the standard horizontal synchronizing pulse. This compared output is supplied to the VCO 61 through a low pass filter 67 as a control voltage.
摘要翻译：目的：为了通过对VCO的振荡输出进行分频来简化结构，从分频输出形成水平同步脉冲，并进一步对其进行分频，以通过与标准相位比较的结果通过输出控制VCO 水平同步脉冲。构成：来自VCO 61的用于不隔行显示的时钟被施加到分频电路62，其中时钟被分频为2fh（标准值），其输出被提供给解码器63，解码输出Pj和Pk 被提取。该输出被馈送到FF64，并且水平同步脉冲被引出。该脉冲施加到T触发器65并且频率除以2/1，该脉冲被提供给相位比较电路66，其中脉冲相位与标准水平同步脉冲的相位相比较。该比较的输出通过作为控制电压的低通滤波器67提供给VCO 61。

100. 发明专利

JPS59148481A Display control circuit 失效
标题翻译：显示控制电路
公开(公告)号：JPS59148481A
公开(公告)日：1984-08-25
申请号：JP2316783
申请日：1983-02-15
申请人： Sony Corp
发明人： MAEDA SATORU , NOGUCHI YASUSHI
IPC分类号： H04N9/00 , G09G1/28 , G09G5/02 , H04N7/173
摘要： PURPOSE: To improve the display speed by making a logical section process only chrominance information not including pattern information.
CONSTITUTION: A code signal BG of background color and a code signal RS of raster color are applied to a selector 13 and a code signal FG of foreground color and said signal BG are compared at a comparator circuit 11. When FG= BG, the signal RS is extracted and fed to a latch 15 and when FG±BG, the signal BG is extracted. Further, a code signal FL of flashing is extracted from a selector 14 only when the flashing is bright and the signal FG is extracted when the flashing is extinguished. A selector 17 is switched by a signal Y with phase synchronism by a display clock DCK and output any of said signals BG, RS, FG and FL.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：通过使逻辑部分仅处理不包括模式信息的色度信息来提高显示速度。构成：将比较电路11将背景颜色的代码信号BG和光栅颜色的代码信号RS施加到选择器13，并将比较电路11比较前景色和信号BG的代码信号FG。当FG = BG时，信号提取RS并将其馈送到锁存器15，并且当FG +或-BG时，提取信号BG。此外，仅当闪烁较亮并且当闪烁熄灭时提取信号FG时，才从选择器14中提取闪烁的代码信号FL。选择器17通过显示时钟DCK的相位同步的信号Y切换，并输出任何所述信号BG，RS，FG和FL。

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