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    • 94. 发明专利
    • NON-SIGNAL DETECTION SYSTEM
    • JPS612456A
    • 1986-01-08
    • JP12170884
    • 1984-06-15
    • HITACHI LTD
    • TAKIYASU YOSHIHIRO
    • H04L25/02H04L1/20H04L25/52
    • PURPOSE:To simplify the constitution of an amplifier and to form a monolithic integrated circuit by connecting an asymmetrical differential amplifier of which input signal DC level is different from a reference voltage, a circuit for forming the center level of the double phase output voltages of the differential amplifier and the average level of one-side outputs and a circuit for detecting the difference of both the levels, to the post-stage of a limit amplifier. CONSTITUTION:Since the rise and fall times of a timing clock signal are rapid, the occupation ratio of the output wave of an asymmetrical amplifier 9 having a reference voltage different from an input signal DC level obtained by inputting a clock having 50% occupation ratio is also about 50% and the average level almost coincides with the center level of the clock. On the other hand, the reference voltage of the asymmetrical amplifier 9 is set up to a low level at the time of no signal, so that its output becomes a high level. Therefore, no signal can be detected by comparing the center level of the output of the asymmetrical amplifier 9 with the average level. For instance, V5 is the reference voltage of the asymmetrical amplifier 9. Figure (b) shows the output of the asymmetrical amplifier 9, and since the output is shifted from the center level of the V5, the output is turned to the high level at the time of no signal.