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1. 发明专利

JP3880394B2 Arbitrary waveform generator 有权
公开(公告)号：JP3880394B2
公开(公告)日：2007-02-14
申请号：JP2001391986
申请日：2001-12-25
申请人：アンリツ株式会社
发明人：剛井上 , 直博渡邉
IPC分类号： G06G7/26

2. 发明专利

JP2005233962A System and method for controlling dynamic waveform resource 审中-公开
标题翻译：用于控制动态波形资源的系统和方法
公开(公告)号：JP2005233962A
公开(公告)日：2005-09-02
申请号：JP2005042094
申请日：2005-02-18
申请人： Agilent Technol Inc , アジレント・テクノロジーズ・インクAgilent Technologies, Inc.
发明人： KOLMAN ROBERT S , HAYHOW REID , SEPTON DAVEN W
IPC分类号： G01R31/3183 , G06F11/26 , G06F19/00 , G06G7/26
CPC分类号： G06G7/26
摘要： PROBLEM TO BE SOLVED: To provide a method and a system for increasing the number of waveforms which a device characterized by its own limited waveform memory capacity can generate.
SOLUTION: This system is provided with a processor 2; an application program 4 executable by the processor 2 requiring the use of the 1st number of waveforms; a waveform table 5 containing the waveform table entry of the 2nd number smaller than the 1st number, which stores a waveform used by the application program 4 an application policy 7 containing waveform sequencing information specific to the application program 4; and a dynamic waveform manager 6 which monitors execution of the application program 4, accesses the application policy 7, to determine the waveform nextly-needed by the application program 4 among the 1st number of waveforms and then load one or more waveforms among those of the 1st number on one or more associated entries among the 2nd number of waveform table entries in the waveform table 5.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于增加以其自身有限的波形存储器容量为特征的装置可以产生的波形数量的方法和系统。解决方案：该系统配有处理器2; 可由处理器2执行的应用程序4，其需要使用第一数量的波形; 波形表5包含小于第1号的第2个数字的波形表项，其存储应用程序4使用的波形，该应用策略7包含应用程序4特有的波形排序信息; 以及动态波形管理器6，其监视应用程序4的执行，访问应用策略7，以确定应用程序4在第一数量波形中随后需要的波形，然后加载一个或多个波形波形表5中第二个波形表项中的一个或多个相关条目上的第一个数字。
版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2001202017A ARBITRARY FUNCTION GENERATING CIRCUIT EMPLOYING SIMPLE COMPUTING ELEMENT AND CIPHERING METHOD USING THE CIRCUIT 失效
公开(公告)号：JP2001202017A
公开(公告)日：2001-07-27
申请号：JP2000009224
申请日：2000-01-18
申请人： NATL AGRICULTURE RES CT MAFF , HIRAFUJI MASAYUKI
发明人： HIRAFUJI MASAYUKI
IPC分类号： G06G7/26 , G09C1/00 , H04K1/00 , H04L9/00
摘要： PROBLEM TO BE SOLVED: To provide a computing circuit which generates complex functions and waveforms employing simple devices. SOLUTION: A nonlinear analog circuit equivalent to a generalized Lotka- Volterra equation is constituted of an analog multiplier, an amplifier and a frequency multiplier and the circuit is operated at a high speed.

4. 发明专利

JP3191678B2 失效
公开(公告)号：JP3191678B2
公开(公告)日：2001-07-23
申请号：JP13904296
申请日：1996-05-31
IPC分类号： G06G7/60 , G06F15/18 , G06G7/26 , G06N99/00

5. 发明专利

JP2741116B2 失效
公开(公告)号：JP2741116B2
公开(公告)日：1998-04-15
申请号：JP14553591
申请日：1991-05-21
IPC分类号： G06F9/44 , G06G7/12 , G06G7/26 , G06N7/02

6. 发明专利

JP2651635B2 失效
公开(公告)号：JP2651635B2
公开(公告)日：1997-09-10
申请号：JP13186991
申请日：1991-05-07
申请人： MIKUNI KK
发明人： MURAJI TETSURO
IPC分类号： G05B13/02 , G06F9/44 , G06G7/26 , G06N7/02

7. 发明专利

JP2544210B2 失效
公开(公告)号：JP2544210B2
公开(公告)日：1996-10-16
申请号：JP27550989
申请日：1989-10-23
申请人： YOKOGAWA ELECTRIC CORP
发明人： TSUNEOKA TAKASHI
IPC分类号： G06G7/26 , H03B28/00

8. 发明专利

JPH0816688A PERIODIC CHAOS GENERATION CIRCUIT BY FREQUENCY CONTROL 失效
公开(公告)号：JPH0816688A
公开(公告)日：1996-01-19
申请号：JP14508294
申请日：1994-06-27
申请人： TANAKA MAMORU
发明人： FUAMU KONKA , TANAKA MAMORU , SHONO KATSUFUSA
IPC分类号： G06G7/26 , H03B29/00
摘要： PURPOSE:To simplify a chaos generation circuit and to realize a small-scaled circuit element by generating a periodic or chaotic waveform by an inverter circuit and a sampling and hold circuit. CONSTITUTION:A sampling hold circuit is composed in a form that a hold capacitor is inserted between the connection point of an inverter circuit composed of a resistor and an MOS transistor connected serially to each other and two serially connected CMOS switch circuits and ground. A periodic or chaotic waveform is generated as the input/output characteristic of the inverter circuit by repeating the operation of turning off a CMOS switch when a CMOS switch out of the two CMOS switches is turned on and applying the control of the sampling frequency of the sampling hold circuit. Therefore, a chaos generation circuit can be simplified and a small-scaled circuit element can be realized.

9. 发明专利

JPH0744641A NON-MONOTONE FUNCTION GENERATION CIRCUIT 失效
公开(公告)号：JPH0744641A
公开(公告)日：1995-02-14
申请号：JP20368193
申请日：1993-07-26
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： MORIE TAKASHI
IPC分类号： G06G7/26 , G06G7/60
摘要： PURPOSE:To easily constitute a circuit approximately generating a function by generating a non-monotone function by more than two circuits of a differential amplifier, a multiplier and a square circuit and a level shift circuit. CONSTITUTION:The multiplier provided between an input and a differential amplifier is a circuit widening the width of the peak of the monotone bounded function obtained by the differential amplifier (monotone bounded function generation circuit) provided on the second stage from the input. The multiplier provided on the lower stage of Fig. (1) is a circuit widening the width of the peak of a unimodal function to be generated in a square circuit (unimodal function generation circuit). The multiplier provided on the back stage of the differential amplifier of Fig. (2) is a circuit controlling the level of the unimodal function. In this case, by two differential amplifiers and the multifiler multiplying the outputs of these differential amplifiers with each other, a function having the same form as the approximate function of the secondary derived function of the monotone bounded function where the level of an input is not 0 in + or -infinity can be generated.

10. 发明专利

JPH06231287A METHOD AND DEVICE FOR GENERATING CHAOS SIGNAL 失效
公开(公告)号：JPH06231287A
公开(公告)日：1994-08-19
申请号：JP3954793
申请日：1993-02-03
申请人： NEW JAPAN RADIO CO LTD , YAMAKAWA RETSU
发明人： KITAMURA MASAYOSHI , YAMAKAWA RETSU
IPC分类号： G06G7/26 , G06F17/10 , H03H17/00 , H03H17/02 , G06F15/31
摘要： PURPOSE:To provide the method and device for generating chaos signals. CONSTITUTION:The output of a delay element 10 at the forefront stage from among delay elements 10-14 connected in series is given to a non-linear function element 30 and the output of other delay elements 11-14 is given to coefficient elements 41-44. The non-linear function element 30 and the coefficient elements 41-44 are added by an addition element 50. The addition result is returned to the delay element 10 at the forefront stage. The operation starts by giving the initial value in a batch from initializing elements 20-24. The delay, non-linear operation, coefficient multiplication and addition are executed repeatedly at the proper time cycle DELTAt. During the while, the non-linear function of the non- linear function element is switched by the signal binarizing the external input signal.

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