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1. 发明专利

JP2006190885A Substrate for layer formation, wiring substrate and its manufacturing method, and semiconductor device and its manufacturing method 有权
标题翻译：用于层形成的基板，布线基板及其制造方法及半导体器件及其制造方法
公开(公告)号：JP2006190885A
公开(公告)日：2006-07-20
申请号：JP2005002659
申请日：2005-01-07
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： MURAI HIDEYA , KIKUCHI KATSU , YAMAMICHI SHINTARO , ORITO NAONORI , NAKANO KAICHIRO , MAEDA KATSUMI , TANAKA DAISUKE , SOEJIMA KOJI , KURITA YOICHIRO
IPC分类号： H01L23/12 , H01L23/32
CPC分类号： H01L2224/16
摘要： PROBLEM TO BE SOLVED: To provide a substrate for layer formation capable of easily separating a wiring layer and stably forming a wiring layer, a wiring substrate and its manufacturing method, and to provide a semiconductor device and its manufacturing method. SOLUTION: There is formed an exfoliation layer composed of resin which contains an elastomer on a support substrate. After forming copper wiring 3 on the exfoliation layer, a via 5 is formed on the copper wiring 3 so that an insulating film 4 may be formed for covering portions other than the upper surface of the via 5. Furthermore, copper wiring 6 connected electrically to the copper wiring 3 through the via 5 is formed on the insulating film 4. Moreover, after forming a via 8 on the copper wiring 6 so that an insulating layer 7 may be formed for covering portions other than the upper surface of the via 8, copper wiring 9 connected electrically to the copper wiring 6 and the via 8 is formed on the insulating film 7. After the support board 1 wherein a wiring layer 11 and a wiring layer 12 are formed is carried out by plasma polymerization in gas containing a fluoridation carbon gas so as to reduce the adhesion power of the exfoliation layer, a wiring substrate 10 is obtained by separating the wiring layer 11 and the wiring layer 12. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够容易地分离布线层并稳定地形成布线层的层形成用基板，布线基板及其制造方法，提供半导体装置及其制造方法。解决方案：在支撑基板上形成包含弹性体的由树脂构成的剥离层。在剥离层上形成铜布线3之后，在铜布线3上形成通孔5，以形成绝缘膜4，以覆盖通孔5的上表面以外的部分。此外，铜布线6电连接到在绝缘膜4上形成通过通孔5的铜布线3.此外，在铜布线6上形成通孔8之后，可以形成用于覆盖通孔8的上表面以外的部分的绝缘层7，在绝缘膜7上形成有与铜布线6和通路8电连接的铜布线9.在其中形成布线层11和布线层12的支撑板1之后，通过在含氟化物的气体中进行等离子体聚合碳气体，以降低剥离层的附着力，通过分离布线层11和布线层12获得布线基板10.（C）2006，JPO＆NCIPI

2. 发明专利

JP2006179952A Manufacturing method of wiring board for mounting semiconductor, and manufacturing method of semiconductor apparatus 有权
标题翻译：用于安装半导体的接线板的制造方法和半导体器件的制造方法
公开(公告)号：JP2006179952A
公开(公告)日：2006-07-06
申请号：JP2006068413
申请日：2006-03-13
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： MURAI HIDEYA , ORITO NAONORI , FUNAYA TAKUO , KIKUCHI KATSU , YAMAMICHI SHINTARO , BABA KAZUHIRO , HONDA KOICHI , HO KEIICHIRO , MATSUI KOJI , MIYAZAKI SHINICHI
IPC分类号： H01L23/12
CPC分类号： H01L2224/48091 , H01L2224/48227 , H01L2924/15312 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide manufacturing methods of a wiring board for mounting a semiconductor and of a semiconductor apparatus which are effective for the increase in terminals and the fine-pitch of terminal gaps due to high-integration, high-speed, and multi-functionalization of semiconductor devices, can mount semiconductor devices especially on both surfaces of a board in a high density and with a high precesion, and is further excellent in reliability. SOLUTION: The wiring board 5 comprises at least an insulation film 1, wiring 2 formed in the insulation film 1, and a plurality of electrode pads 4 which are made mutually conductive by the wiring 2 and vias 3. The electrode pads 4 are disposed on the front and back surfaces of the insulation film 1 with the surfaces of the pads exposed and at least a part of the sides of the electrode pads embedded in the insulation film 1. The insulation film 1 is formed by forming respective electrode pads 4 on two metal sheets, stacking insulation layers and wiring on the electrode pads 4 and the metal plates, laminating, and integrating the insulation layers, and then removing the metal sheets. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供用于安装半导体的布线板和半导体装置的制造方法，其对于增加端子和由于高集成度而导致的端子间隙的微细间距高效率和半导体器件的多功能化，可以以高密度和高密度安装半导体器件，特别是在板的两个表面上，并且其可靠性更好。解决方案：布线板5至少包括绝缘膜1，形成在绝缘膜1中的布线2和由布线2和通孔3相互导电的多个电极焊盘4.电极焊盘4 设置在绝缘膜1的前表面和后表面上，其中焊盘的表面暴露，并且电极焊盘的至少一部分侧面嵌入绝缘膜1中。绝缘膜1通过形成相应的电极焊盘 4的两个金属片，堆叠绝缘层和电极焊盘4和金属板上的布线，层压并整合绝缘层，然后去除金属片。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2007250712A Semiconductor device and method of manufacturing same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007250712A
公开(公告)日：2007-09-27
申请号：JP2006070347
申请日：2006-03-15
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： MURAI HIDEYA , HONDA KOICHI , KIKUCHI KATSU , SOEJIMA KOJI , KYOGOKU YOSHITAKA , YAMAMICHI SHINTARO
IPC分类号： H01L21/60 , H01L23/12
CPC分类号： H01L2224/13
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device excellent in reliability in which breakage of a joint is prevented by relaxing thermal stress resulting from difference in thermal expansion coefficient between a substrate and a semiconductor chip, efficiently and to provide a method of manufacturing the same. SOLUTION: In the semiconductor device where a substrate 21 provided with a plurality of second pads 23 on the semiconductor chip mounting side, and a semiconductor chip 11 having a resin layer 12 provided on the surface and a plurality of first pads 13 provided on the resin layer 12 are connected electrically by flip-chip connection, at least one of the first pads 13 of the semiconductor chip 11 inclines or deforms and the distance between the first pad 13 and the surface of the semiconductor chip 11 is set longer at the peripheral side end of the semiconductor chip 11 than at the central end of the semiconductor chip 11. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种可靠性优异的半导体器件，其通过缓解由基板和半导体芯片之间的热膨胀系数的差异导致的热应力而防止接头断裂，并提供一种方法制造相同。解决方案：在半导体器件中，在半导体芯片安装侧设置有多个第二焊盘23的基板21和设置在表面上的树脂层12的半导体芯片11和设置有多个第一焊盘13的半导体装置在树脂层12上通过倒装芯片连接电连接，半导体芯片11的至少一个第一焊盘13倾斜或变形，第一焊盘13与半导体芯片11的表面之间的距离设定得更长半导体芯片11的外围侧端部比半导体芯片11的中心端。（C）2007年，JPO＆INPIT

4. 发明专利

JP2007096337A Wiring substrate for mounting semiconductor, semiconductor package, and its manufacturing method 审中-公开
标题翻译：用于安装半导体的接线基板，半导体封装及其制造方法
公开(公告)号：JP2007096337A
公开(公告)日：2007-04-12
申请号：JP2006313640
申请日：2006-11-20
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： MURAI HIDEYA , ORITO NAONORI , FUNAYA TAKUO , KIKUCHI KATSU , YAMAMICHI SHINTARO , BABA KAZUHIRO , HONDA KOICHI , HO KEIICHIRO , MATSUI KOJI , MIYAZAKI SHINICHI
IPC分类号： H01L23/12 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a wiring substrate for mounting semiconductor which is effective for the high integration of a semiconductor device, high speed, or increase in terminal by multifunction, and the narrow pitch of a distance between terminals, in which the semiconductor device can be mounted with high density and high accuracy specifically on the both surfaces of a substrate, and which is excellent also in reliability, its manufacturing method, and a semiconductor package.
SOLUTION: A wiring substrate 5 for mounting semiconductor is a wiring substrate comprising at least an insulating film 1, wiring 2 formed in the insulating film 1, and a plurality of electrode pads 4 conducted by the wiring 2 and a via 3. The electrode pad 4 is prepared on the front and back surfaces of the insulating film 1 such that the front surface is exposed. At least a part of the side surface of the electrode pad is embedded in the insulating film 1. The insulating film 1 can be formed by forming the electrode pads 4 on two sheets of metal plates, laminating the insulating layer and the wiring on the electrode pad 4 and each metal plate, pasting the insulating layer together and unifying the layer, and removing the metal plate.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种半导体装置的布线基板，其有效用于半导体器件的高集成度，高速度或多功能的端子增加，以及端子之间的距离的窄间距，其中半导体器件可以特别地在基板的两个表面上高密度和高精度地安装，并且在可靠性，其制造方法和半导体封装中也是优异的。解决方案：用于安装半导体的布线基板5是至少包括绝缘膜1，形成在绝缘膜1中的布线2和由布线2和通孔3传导的多个电极焊盘4的布线基板。在绝缘膜1的前表面和后表面上制备电极焊盘4，使得前表面露出。电极焊盘的侧面的至少一部分嵌入在绝缘膜1中。绝缘膜1可以通过在两片金属板上形成电极焊盘4而形成，在电极上层压绝缘层和布线垫4和每个金属板，将绝缘层粘贴在一起并使层合并，并移除金属板。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2006228919A Wiring board, semiconductor device, and their manufacturing method 有权
标题翻译：接线板，半导体器件及其制造方法
公开(公告)号：JP2006228919A
公开(公告)日：2006-08-31
申请号：JP2005040062
申请日：2005-02-17
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： KIKUCHI KATSU , YAMAMICHI SHINTARO , MURAI HIDEYA , ORITO NAONORI , NAKANO KAICHIRO , MAEDA KATSUMI , TANAKA DAISUKE , KURITA YOICHIRO , SOEJIMA KOJI
IPC分类号： H05K3/20 , H01L23/12 , H01L23/14
CPC分类号： H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2224/83005 , H01L2924/01322 , H01L2924/15192 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a wiring board wherein a water system process is used to stably form a wiring structural body on a supporting substrate, and the wiring structural body can be easily peeled off from the supporting substrate. SOLUTION: The wiring board 10 includes a supporting substrate 11 and a wiring structural body 17 which is arranged on the supporting substrate 11 with an adhesion layer 24 in-between. The adhesion layer 24 is comprised of a first layer 12 made of a water-soluble material, and a second layer 13 which is formed so as to cover the entire surface of the first layer 12 and is made of a waterproof material. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种布线板，其中使用水系统工艺来在支撑基板上稳定地形成布线结构体，并且布线结构体可以容易地从支撑基板剥离。解决方案：布线板10包括支撑基板11和布置在支撑基板11上的布线结构体17，其间具有粘合层24。粘合层24由水溶性材料制成的第一层12和形成为覆盖第一层12的整个表面并由防水材料制成的第二层13构成。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2006032600A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2006032600A
公开(公告)日：2006-02-02
申请号：JP2004208375
申请日：2004-07-15
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： KIKUCHI KATSU , YAMAMICHI SHINTARO , MURAI HIDEYA , HONDA KOICHI , SOEJIMA KOJI , MIYAZAKI SHINICHI
IPC分类号： H01L23/522 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L23/12 , H01L23/52 , H01L27/04
CPC分类号： H01L23/528 , H01L23/3114 , H01L23/5286 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which has an enormous wiring structure to mitigate stress generated in a fine wiring structure, and operates at a large drive current and a high frequency with high reliability.
SOLUTION: A fine wiring structure 12 by laminating a first wiring layer and a first insulating layer alternately is provided on a semiconductor substrate 11, and a first enormous wiring structure 13a is provided by laminating a second wiring layer 15 having a thickness which is twice or more the first wiring layer and a second insulating layer 14, alternately. Further, a second enormous wiring structure 13b is provided on the first enormous wiring structure 13a by laminating a third wiring layer 17 having a thickness which is twice or more the first wiring layer and a third insulating layer 16 having an elastic modulus smaller than the second insulating layer 14 at 25 °C alternately. Thus, stress generated in the semiconductor device after being mounted to a mounting board is effectively mitigated in the first enormous wiring structure 13a and the second enormous wiring structure 13b, and stress applied to the fine wiring structure 12 can be reduced.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有巨大布线结构以减轻精细布线结构中产生的应力的半导体器件，并以高可靠性的大驱动电流和高频工作。解决方案：通过在半导体衬底11上设置层叠第一布线层和第一绝缘层的精细布线结构12，并且通过层叠具有厚度的第二布线层15来提供第一巨大布线结构13a 是第一布线层和第二绝缘层14的两倍以上。此外，通过层叠第一布线层的两倍以上的厚度的第三布线层17和弹性模量小于第二布线层的第三绝缘层16，在第一布线结构13a上设置第二大布线结构13b 绝缘层14交替地在25℃。因此，在第一巨大布线结构13a和第二巨大布线结构13b中，在安装到安装板上之后在半导体器件中产生的应力被有效地减轻，并且可以减小施加到精细布线结构12的应力。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2009004813A Wiring substrate for mounting semiconductor 审中-公开
标题翻译：用于安装半导体的接线基板
公开(公告)号：JP2009004813A
公开(公告)日：2009-01-08
申请号：JP2008243381
申请日：2008-09-22
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： MURAI HIDEYA , ORITO NAONORI , FUNAYA TAKUO , KIKUCHI KATSU , YAMAMICHI SHINTARO , BABA KAZUHIRO , HONDA KOICHI , HO KEIICHIRO , MATSUI KOJI , MIYAZAKI SHINICHI
IPC分类号： H01L23/12 , H05K3/46
CPC分类号： H01L2221/68345 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/15312 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a wiring substrate for mounting semiconductor which is effective for the high integration of a semiconductor device, high speed, or increase in terminal by multifunctionalities, and the narrow pitch of a distance between terminals, in which the semiconductor device can be mounted at high density and high accuracy, specifically on both the surfaces of a substrate, and which is superior also in reliability. SOLUTION: The wiring substrate 5 for mounting semiconductors includes, at least an insulating film 1, wires 2 formed in the insulation film 1, and a plurality of electrode pads 4 that electrically connect to the wires 2 through vias 3. The electrode pads 4 are provided, to have their surfaces exposed to both the front surface and the backside of the insulation film 1, and at least part of the side surface of the electrode pads is embedded in the insulating film 1. The insulating film 1 is formed, by forming electrode pads 4 on the respective two metal plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad 4, and making the insulation layers adhere to each other for integration, and thereafter, removing the metal plates. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种半导体安装用布线基板，其能够通过多功能性实现半导体器件的高集成度，高速度或端子的增加，以及端子之间的距离的窄间距，其中半导体器件可以以高密度和高精度安装，特别是在基板的两个表面上，并且其可靠性也优异。解决方案：用于安装半导体的布线基板5至少包括绝缘膜1，形成在绝缘膜1中的布线2，以及多个通过通孔3电连接到布线2的电极焊盘4。提供垫4以使其表面暴露于绝缘膜1的前表面和后侧，并且电极焊盘的至少一部分侧表面被嵌入绝缘膜1中。形成绝缘膜1 通过在相应的两个金属板上形成电极焊盘4，然后在相应的金属板上层叠绝缘层和电线以覆盖电极焊盘4，并且使绝缘层彼此粘合以一体化，然后除去金属板。版权所有（C）2009，JPO＆INPIT

8. 发明专利

JP2008306071A Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008306071A
公开(公告)日：2008-12-18
申请号：JP2007153293
申请日：2007-06-08
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： MORI KENTARO , YAMAMICHI SHINTARO , MURAI HIDEYA , FUNAYA TAKUO , KAWANO MASAYA , MAEDA TAKEHIKO , SOEJIMA KOJI
IPC分类号： H01L23/12
CPC分类号： H01L21/6835 , H01L23/5389 , H01L23/544 , H01L24/19 , H01L24/24 , H01L2221/68345 , H01L2223/5442 , H01L2223/54426 , H01L2223/54473 , H01L2223/54486 , H01L2224/04105 , H01L2224/24226 , H01L2224/32225 , H01L2224/73267 , H01L2224/82039 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01041 , H01L2924/01046 , H01L2924/01047 , H01L2924/01056 , H01L2924/01057 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/12044 , H01L2924/15174 , H01L2924/15788 , H01L2924/181 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3011 , Y10S438/977 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of achieving high density, thin shape and low cost, which achieves chip mounting with high precision, which needs no preparation of position marks on a base material at the time of chip mounting on the base material in a manufacturing process, and which can make removing of the base material easy, and a method for manufacturing the same. SOLUTION: A transparent substrate 23 is arranged on a support substrate 21 provided with position marks 22, and a lifting material 24 is provided thereon. On the lifting material 24, a semiconductor element 11 is arranged so that electrode elements 13 are upside, and, thereafter, the support substrate 21 is removed. Subsequently, after an insulating resin 12 is formed on the lifting material 24 so as to cover the semiconductor element 11, vias 14, a wiring layer 15, an insulating layer 16, external terminals 17 and a solder resist 18 are formed. Thereafter, the transparent substrate 23 is removed from the semiconductor device by the lifting material 24. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供能够实现高密度，薄形状和低成本的半导体器件，其实现了高精度的芯片安装，在芯片安装时不需要在基材上准备位置标记在制造工艺中的基材上，并且能够容易地除去基材，以及其制造方法。解决方案：在设置有位置标记22的支撑基板21上设置透明基板23，并且在其上设置提升材料24。在提升材料24上，配置半导体元件11，使得电极元件13是上侧，之后移除支撑基板21。随后，在提升材料24上形成绝缘树脂12以覆盖半导体元件11，通孔14之后，形成布线层15，绝缘层16，外部端子17和阻焊剂18。此后，透明基板23由提升材料24从半导体器件移除。版权所有（C）2009，JPO＆INPIT

9. 发明专利

JP2006049819A Wiring substrate for mounting semiconductor, its manufacturing method, and semiconductor package 有权
标题翻译：用于安装半导体的布线基板及其制造方法和半导体封装
公开(公告)号：JP2006049819A
公开(公告)日：2006-02-16
申请号：JP2005138450
申请日：2005-05-11
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： MURAI HIDEYA , ORITO NAONORI , FUNAYA TAKUO , KIKUCHI KATSU , YAMAMICHI SHINTARO , BABA KAZUHIRO , HONDA KOICHI , HO KEIICHIRO , MATSUI KOJI , MIYAZAKI SHINICHI
IPC分类号： H01L23/12
CPC分类号： H01L21/4857 , H01L23/49822 , H01L23/49833 , H01L23/5383 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L2221/68345 , H01L2224/16225 , H01L2224/45144 , H01L2224/48227 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/15312 , H01L2924/1532 , H01L2924/181 , H05K3/007 , H05K3/205 , H05K3/28 , H05K3/4614 , H05K3/4682 , H05K2201/0376 , H05K2203/0152 , H05K2203/061 , H01L2224/05599 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a wiring substrate for mounting a semiconductor which is effective in the increase of terminal and close narrowness of space between terminals due to the high integration, high speedup, and multi-functionalization of a semiconductor device, and which can particularly mount semiconductors on both sides of the substrate in high density and with high accuracy, and which is excellent in reliability too; to provide its manufacturing method; and to provide a semiconductor package. SOLUTION: The wiring substrate 5 for mounting a semiconductor is composed of at least an insulating film 1, wiring 2 formed in the insulating film 1, and a plurality of electrode pads 4 connected with the wiring 2 and a via 3. The electrode pad 4 is located on both sides of the surface/back with the surface exposed, and at least a part of side of the electrode pad is buried in the insulating film 1. After the electrode pads 4 are formed on the two sheets of metal plate and then the insulating layer and wiring are laminated on the electrode pad 4 and each of metal plates, the insulating layer 1 is laminated to be united, then, the insulating layer 1 can be formed by removing the metal plate. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：为了提供一种用于安装半导体的布线基板，其由于半导体器件的高集成度，高加速度和多功能化而在端子间增加并且端子之间的空间狭窄，所以有效，并且可以以高密度和高精度特别地在基板的两侧上安装半导体，并且其可靠性也优异; 提供其制造方法; 并提供半导体封装。解决方案：用于安装半导体的布线基板5至少由绝缘膜1，形成在绝缘膜1中的布线2和与布线2和通孔3连接的多个电极焊盘4构成。电极焊盘4位于表面/背面的两侧，表面露出，并且电极焊盘的至少一部分侧面被埋在绝缘膜1中。在电极焊盘4形成在两片金属然后将绝缘层和布线层叠在电极焊盘4和每个金属板上，将绝缘层1层合在一起，然后通过去除金属板来形成绝缘层1。版权所有（C）2006，JPO＆NCIPI

10. 发明专利

JP2005327780A Wiring board and semiconductor package using same 有权
标题翻译：使用相同的接线板和半导体封装
公开(公告)号：JP2005327780A
公开(公告)日：2005-11-24
申请号：JP2004142133
申请日：2004-05-12
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： ORITO NAONORI , KIKUCHI KATSU , MURAI HIDEYA , BABA KAZUHIRO , HONDA KOICHI , HO KEIICHIRO
IPC分类号： H01L23/12 , H01L21/48 , H01L21/68 , H01L23/14 , H01L23/498 , H01L25/065 , H05K1/03 , H05K1/11 , H05K3/20 , H05K3/42
CPC分类号： H01L23/49816 , H01L21/4857 , H01L21/6835 , H01L23/145 , H01L23/49822 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2221/68345 , H01L2224/16225 , H01L2224/16237 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/83102 , H01L2224/92125 , H01L2225/0651 , H01L2225/06517 , H01L2225/06586 , H01L2924/00014 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H05K1/0366 , H05K3/205 , H05K3/423 , H05K2201/0376 , H05K2201/068 , H05K2203/0733 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To provide a wiring board which enables various devices, such as semiconductor devices or the like, to be high densely mounted thereon, facilitates higher speed, higher density and finer wiring, and has excellent reliability; and to provide a semiconductor package using the same. SOLUTION: A base dielectric 7 is provided on the wiring board 13. The base dielectric has a film thickness of 20 to 100 μm. A reinforcing fiber comprising glass or aramid is contained in a heat resistant resin that has glass transition temperature of 150°C or over. Moreover, the wiring board has physical properties as follows: (1) assuming that modulus of elasticity is D T when thermal expansion ratio in the thickness direction is 90 ppm/K or below and when temperature is T°C, and breaking strength is H T when temperature is TC, then (2) D 23 ≥5 GPa, (3) D 150 ≥2.5 GPa, (4) (D -65 /D 150 )≤3.0, (5) H 23 ≥140 MPa, and (6) (H -65 /H 150 )≤2.3. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供使诸如半导体器件等的各种器件高密度地安装在其上的布线板，有利于更高速度，更高密度和更精细的布线，并且具有优异的可靠性; 并提供使用其的半导体封装。解决方案：基底电介质7设置在布线板13上。基底电介质具有20至100μm的膜厚度。包含玻璃或芳族聚酰胺的增强纤维包含在玻璃化转变温度为150℃以上的耐热性树脂中。此外，布线板具有以下物理性质：（1）当厚度方向的热膨胀率为90ppm / K以下且当温度为T°时，假定弹性模量为D T C，当温度为TC时断裂强度为H T ，则（2）D 23 ≥5GPa，（3）D 150 ≥ 2.5GPa，（4）（D -65 / D 150 ）≤3.0，（5）H 23 ≥140MPa，（6 ）（H -65 / H 150 ）≤2.3。版权所有（C）2006，JPO＆NCIPI

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