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1. 发明专利

JP2004303420A Device having nonvolatile memory 审中-公开
公开(公告)号：JP2004303420A
公开(公告)日：2004-10-28
申请号：JP2004222690
申请日：2004-07-30
申请人： Hitachi Ulsi Systems Co Ltd , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社日立超エル・エス・アイ・システムズ
发明人： SEKI KOICHI , WADA TAKESHI , MUTO TADASHI , KUBOTA YASURO , SHOJI KAZUYOSHI
IPC分类号： G11C16/02
摘要： PROBLEM TO BE SOLVED: To provide a device having a nonvolatile memory improved in operability. SOLUTION: The device is provided with a bus and a plurality of memories one of which is a nonvolatile memory, a processor and input output terminals. All of them are connected to the bus. The nonvolatile memory receives a plurality of control signals from the processor, executes erase and erase verify operations for the memory cells that are internally specified and automatically conducts erase operations when the erasing is insufficient. Having transmitted erasing signals to the nonvolatile memory, the processor conducts discrimination to determine whether the erasing mode is completed or not based on the information outputted to the bus from the nonvolatile memory. During the period, i.e., after the erase signals are transmitted to the nonvolatile memory and till the erasing mode is completed at the nonvolatile memory, accesses are made to the memories in order to input data from the external through the input output terminals. COPYRIGHT: (C)2005,JPO&NCIPI

2. 发明专利

JP2004134085A System, and device having nonvolatile memory 有权
公开(公告)号：JP2004134085A
公开(公告)日：2004-04-30
申请号：JP2004029156
申请日：2004-02-05
申请人： Hitachi Ulsi Systems Co Ltd , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社日立超エル・エス・アイ・システムズ
发明人： SEKI KOICHI , WADA TAKESHI , MUTO TADASHI , KUBOTA YASURO , SHOJI KAZUYOSHI
IPC分类号： G06F12/16 , G11C16/02
摘要： PROBLEM TO BE SOLVED: To provide a computer system which is easy to use. SOLUTION: A computer system is constituted of a nonvolatile semiconductor memory device having a writing mode in which information is written in a memory cell, a read-out mode in which information of the memory cell is read out, an erasing mode in which erasing operation applying voltage for keeping threshold voltage of the memory cell in a prescribed range and verifying operation reading out a state of the threshold voltage of the memory cell are performed, and a data polling mode function outputting a state of the verifying operation to the outside, and a processor. COPYRIGHT: (C)2004,JPO

3. 发明专利

JP2006048930A Nonvolatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：JP2006048930A
公开(公告)日：2006-02-16
申请号：JP2005310935
申请日：2005-10-26
申请人： Hitachi Ulsi Systems Co Ltd , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社日立超エル・エス・アイ・システムズ
发明人： SEKI KOICHI , WADA TAKESHI , MUTO TADASHI , KUBOTA YASURO , SHOJI KAZUYOSHI
IPC分类号： G11C16/02
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile memory device improved in operability. SOLUTION: The nonvolatile memory device has a nonvolatile memory array in which a plurality of nonvolatile memory cells are arranged in a array state, a voltage generating circuit, and an input/output terminal. The nonvolatile memory is divided into a plurality of blocks, a block of 1 can be selected in accordance with an inputted address signal out of the plurality of blocks in accordance with an address signal inputted from the outside. The voltage generating circuit can generate erasing voltage in erasing operation of data stored in the nonvolatile memory cell. A first state signal is outputted to the input/output terminal during a term in which erasing voltage is supplied to the nonvolatile memory cell existing in the selected block of 1 and erasing of data stored in the nonvolatile memory cell existing in the selected block of 1 is completed. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供可操作性提高的非易失性存储装置。解决方案：非易失性存储器件具有非易失性存储器阵列，其中多个非易失性存储单元被布置成阵列状态，电压产生电路和输入/输出端子。非易失性存储器被分成多个块，根据从外部输入的地址信号，可以根据多个块中的输入的地址信号来选择1的块。电压产生电路可以在存储在非易失性存储单元中的数据的擦除操作中产生擦除电压。在将擦除电压提供给存在于所选择的块1中的非易失性存储器单元并擦除存储在选定块1中的非易失性存储单元中的数据的项期间，将第一状态信号输出到输入/输出端子完成了。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2006041818A Semiconductor device having digital interface, memory element and memory module 有权
标题翻译：具有数字接口，存储器元件和存储器模块的半导体器件
公开(公告)号：JP2006041818A
公开(公告)日：2006-02-09
申请号：JP2004217509
申请日：2004-07-26
申请人： Elpida Memory Inc , Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： OSAKA HIDEKI , NISHIO YOJI , SENBA SEIJI , SHOJI KAZUYOSHI
IPC分类号： H04L7/02 , H03K5/00 , H03K5/135
CPC分类号： H03K5/082 , H03K5/135
摘要： PROBLEM TO BE SOLVED: To provide an LSI in which the setting of a delay amount for reducing jitter dependent on data pattern can be adjusted automatically for each device by a receiver at an interface. SOLUTION: Since data pattern dependent jitter can be predicted from a previous state, the state of data received by a receiver is held and timing for taking in the input data is adjusted based on the held state and the inputted data. On the other hand, pulse data of a 1 cycle interval and a 2 cycle interval are transmitted and received as test data to/from a driver as an adjusting mechanism in the receiver for determining a delay amount dependent on the mounting state. An automatic adjusting mechanism for determining a delay amount optimal to the system from the difference of rising and falling times of pulses having different pulse widths is provided. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种LSI，其中可以通过接口处的接收机自动地针对每个设备来调整用于减少依赖于数据模式的抖动的延迟量的设置。解决方案：由于可以从先前状态预测数据模式相关的抖动，所以保持由接收机接收的数据的状态，并且基于保持状态和输入的数据调整用于接收输入数据的定时。另一方面，1周期间隔和2周期间隔的脉冲数据作为测试数据作为测试数据作为测试数据作为接收机中的调整机构发送和接收，用于根据安装状态确定延迟量。提供了一种用于根据具有不同脉冲宽度的脉冲的上升和下降时间的差确定对系统最佳的延迟量的自动调整机构。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2009303245A Semiconductor device with digital interface 有权
标题翻译：具有数字接口的半导体器件
公开(公告)号：JP2009303245A
公开(公告)日：2009-12-24
申请号：JP2009216805
申请日：2009-09-18
申请人： Elpida Memory Inc , Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： OSAKA HIDEKI , NISHIO YOJI , SENBA SEIJI , SHOJI KAZUYOSHI
IPC分类号： H04L7/02 , G06F3/00 , H03K5/00 , H03K5/135 , H04L25/03
摘要： PROBLEM TO BE SOLVED: To provide an LSI, for reducing jitter depending on a data pattern by using a receiver of an interface, which is capable of automatically adjusting setting of a delay amount for reduction. SOLUTION: In a semiconductor device, since a previous state of data pattern dependent jitter is predictable, a state of data received by a receiver is held and timing to capture input data is adjusted from the held state and from input data. As an adjustment mechanism inside the receiver for determining a delay amount depending on a mounting form, pulse data at intervals of one cycle and pulse data at intervals of two cycles are transmitted/received from a driver as a test pattern. An automatic adjustment mechanism for determining a delay amount optimal for a system from a rising and falling time difference of pulses having different pulse widths, is provided. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种用于通过使用能够自动调整用于减小的延迟量的设置的接口的接收器来减少根据数据模式的抖动的LSI。解决方案：在半导体器件中，由于数据模式相关抖动的先前状态是可预测的，因此保持由接收器接收的数据的状态，并且从保持状态和输入数据调整捕获输入数据的定时。作为用于根据安装形式确定延迟量的接收器内的调节机构，以一个周期的间隔的脉冲数据和以两个周期的间隔的脉冲数据作为测试图案从驾驶员发送/接收。提供了一种用于从具有不同脉冲宽度的脉冲的上升和下降时间差确定系统最优的延迟量的自动调整机构。版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2008004853A Laminated semiconductor device, and module 审中-公开
标题翻译：层压半导体器件和模块
公开(公告)号：JP2008004853A
公开(公告)日：2008-01-10
申请号：JP2006174687
申请日：2006-06-26
申请人： Elpida Memory Inc , Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： UEMATSU YUTAKA , OSAKA HIDEKI , SHOJI KAZUYOSHI , NISHIO YOJI , HIROSE YUKITOSHI , ITAYA SATORU
IPC分类号： H01L25/065 , H01L23/12 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/16145 , H01L2924/01055
摘要： PROBLEM TO BE SOLVED: To provide a technique contributing to an improvement of power supply efficiency to an upper layer semiconductor chip, reduction of power supply noise interference between upper and lower semiconductor chips, attainment of the low power supply noise, and high speed operation of a laminated semiconductor device (CoC).
SOLUTION: In the laminated semiconductor device, an interposer 11 is inserted between laminated semiconductor chips 1, 1. The interposer 11 has a feature of its being a high dielectric material such as ceramic whereby the intereposer enjoys both of an electric charge storage function by high capacitance, and of small size filter function. Use of a ceramic interposer having such functions ensures an improvement of power supply capability to the upper layer semiconductor chip noise interference reduction between the upper and lower semiconductor chips.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种有助于提高上层半导体芯片的电源效率的技术，降低上下半导体芯片之间的电源噪声干扰，实现低电源噪声和高层叠半导体器件（CoC）的快速操作。解决方案：在层叠半导体器件中，插入层11插入层叠的半导体芯片1,1之间。插入件11具有诸如陶瓷之类的高介电材料的特征，由此，插入器既具有电荷存储功能由高电容和小尺寸滤波功能。使用具有这种功能的陶瓷插入件确保了上层半导体芯片对上半导体芯片和下半导体芯片之间的噪声干扰降低的电力供应能力的改善。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2007219930A Simulation method and program 审中-公开
标题翻译：模拟方法与程序
公开(公告)号：JP2007219930A
公开(公告)日：2007-08-30
申请号：JP2006041009
申请日：2006-02-17
申请人： Elpida Memory Inc , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立超エル・エス・アイ・システムズ
发明人： NISHIO YOJI , SENBA SEIJI , AOKI HIYAKUGOUKO , SHOJI KAZUYOSHI , MATSUO KOJI , OTSUKA MARIKO , IKEMATSU RYUICHI , NONOYAMA SADAHIRO , FUJII YOSHIE
IPC分类号： G06F17/50 , G01R31/28
CPC分类号： G06F17/5009
摘要： PROBLEM TO BE SOLVED: To provide a simulation method allowing setting of a parameter related to an input/output characteristic on a user side about a memory having a plurality of chips.
SOLUTION: The simulation method has steps of: selecting one from a plurality of parameters related to the input/output characteristic; determining whether to set selection by a comment symbol for preventing execution of a corresponding line or to set the selection by an identification code that is an identifier common to the chips set to the same selection, to the setting line provided in a file for setting the necessary selection from a plurality of pieces of the selection of the selected parameter; deleting the comment symbol of the setting line of the necessary selection of the plurality of pieces of the selection and making the setting line effective when setting the selection by the comment symbol, and replacing the identification code included in the setting line with information for setting the necessary selection when setting the selection by the identification code; and executing simulation.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种允许在具有多个芯片的存储器上设置与用户侧的输入/输出特性有关的参数的模拟方法。解决方案：模拟方法具有以下步骤：从与输入/输出特性相关的多个参数中选择一个; 确定是否通过用于防止相应行的执行的注释符号来设置选择，或者通过作为设置为相同选择的芯片共有的标识符的识别码将选择设置到设置在用于设置从所选择的参数的多个选择中进行必要的选择; 删除多条选择的必要选择的设定行的注释符号，并且在通过注释符号设置选择时使设置行有效，并且将包括在设置行中的识别码替换为用于设置通过识别码设置选择时的必要选择; 并执行仿真。版权所有（C）2007，JPO＆INPIT

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