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1. 发明专利

JPS5537626A LOAD DECENTRALIZATION SYSTEM 失效
公开(公告)号：JPS5537626A
公开(公告)日：1980-03-15
申请号：JP10956578
申请日：1978-09-08
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： OKAJIMA KEISUKE , KIN KATSUYOSHI
IPC分类号： G06F15/16 , G05D3/12 , G06F15/00 , G06F15/177
摘要： PURPOSE:To decentralize loads evenly by allowing a job schedule processor to register a request of a job to be executed to a queue on a common memory and each processor to receive and execute this job request. CONSTITUTION:Assigned job schedule processor PC210 links at a certain point in time a job request to be executed to job request queue 310 on common memory 300. Other PCs 220 and 230 fetch and execute sequentially jobs from queue 310 and then move to next job requests. On finishing a scheduled job, PC 210 also fetches and executes a job request from queue 310 as well as other PCs 220 and 230. In this way, after each job is finished, each PC fetches a next job request at random, so that loads will be decentralized on the whole.

2. 发明专利

JPS60245056A EXPANDING METHOD OF BUFFER MEMORY BY POINTER DYNAMIC CONTROL 失效
公开(公告)号：JPS60245056A
公开(公告)日：1985-12-04
申请号：JP10053184
申请日：1984-05-21
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： WANAMI MASAO , HIGASHIYAMA FUKUO , KIN KATSUYOSHI , SANO YUKIO
IPC分类号： G06F12/02 , G06F5/06 , G06F12/06 , G06F13/10 , G06F13/38
摘要： PURPOSE:To obtain the expanding method of the buffer memory by the pointer dynamic control by handling numbers of data and using the buffer memory of memory size suitable to respective systems. CONSTITUTION:When the number of planes of the buffer memory 10 is increased, the expansion is possible in normal order where storage point 2 > readout pointer 3. The expansion is impossible in inverted order where storage pointer 2

3. 发明专利

JPS54159109A REGULATION SYSTEM IN ELECTRONIC EXCHANGER IN MULTIPROCESSOR SYSTEM 失效
公开(公告)号：JPS54159109A
公开(公告)日：1979-12-15
申请号：JP6760578
申请日：1978-06-07
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： MORITA SHIGEO , KIN KATSUYOSHI
IPC分类号： H04M3/22 , H04Q3/545
摘要： PURPOSE:To regulate the effective and suitable connection, or the call, by turning on and off the regulation display unit through the regulation and detection with the logic including the accessing of a given area for the local memory fixedly. CONSTITUTION:The central control unit CCP interpretes the information from the peripheral control unit PCP1, for example, and performs the selection processing for the output path such as the selection of the outgoing trunk specified, if it is the number from the preceeding station received and stored in the incoming trunk IRT via the incoming trunk ICT. Further, it is regulated and detected fixedly with the logic including the accessing of a given area of the local memory LM, to turn on and off the regulation and display unit, and if the regulated request is OFF, normal connecting processing is made, and if it is ON, the call is connected to the talkey unit to allow the anouncement of a given message. Thus, effective and suitable connection or regulation of outgoing call can be made.

4. 发明专利

JPH07250099A METHOD FOR MAKING SERVICE CONTROL PART OF EXCHANGE PROGRAM BETWEEN ATM AND STM COMMON 失效
公开(公告)号：JPH07250099A
公开(公告)日：1995-09-26
申请号：JP3830794
申请日：1994-03-09
申请人： NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD , OKI ELECTRIC IND CO LTD , NEC CORP
发明人： KOSHIRO YOSHIHARU , NAKAMURA HIDEFUMI , KAI TOSHIHIRO , KIN KATSUYOSHI , MIZUNO MITSUYUKI , IIZUKA TADASHI , NAKAJIMA SHINICHI
IPC分类号： H04M3/42 , H04L12/28 , H04L12/64 , H04L12/70 , H04M3/00
摘要： PURPOSE:To apply a service control program for N-ISDN in an STM exchange to the service control program for the line emulation of B-ISDN in an ATM exchange by making the service control program of the ATM exchange and STM exchange common. CONSTITUTION:Hierarchical structures, such as a resource hierarchy, a service hierarchy, etc., are applied, the differences of the signal procedures of interfaces with a relay network and subscribers in ATM and STM are absorbed or generated in subscriber and relay control resources and a common signal procedure is defined. Also, object-oriented design is adopted to information inside signals and access to information elements inside the signals is performed through a method. Thus, the format of the information elements is concealed and the different parts of signal analysis, route translation and charging are turned to independent objects for each service.

5. 发明专利

JPS5628592A TIME CONTROL SYSTEM 失效
公开(公告)号：JPS5628592A
公开(公告)日：1981-03-20
申请号：JP10427279
申请日：1979-08-16
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： MANABE SHIROU , MORITA SHIGEO , KIN KATSUYOSHI
IPC分类号： G06F1/14 , G06F15/16 , H04Q3/545
摘要： PURPOSE:To make it possible that the processor of a processor group gets aware of the time by accessing a timing circuit which can be accessed from the processor group commonly, by providing this timing circuit. CONSTITUTION:Central control units 401-40n have not timing circuits in their processors; and in respect to programs started at determined times by central control units above, they transmit order to the timing circuit, which can be accessed by central processing units above commonly to get aware of the time, each time the executing program is completed in central control units, and the program to be started at the time is caused to run. That is, central control units 401-40n transmit order to timing circuit 90 through interprocessor bus 70, communication control unit 80, and peripheral bus 100. The time is transmitted to bus 100 and reaches central control units 401-40n through communication control unit 80 and processor bus 70.

6. 发明专利

JPS5537060A TEST METHOD FOR EXCHANGE SYSTEM 失效
公开(公告)号：JPS5537060A
公开(公告)日：1980-03-14
申请号：JP11031378
申请日：1978-09-08
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： ENDOU KAZUMI , SEIKE KENJI , HORI YOSHINORI , KIN KATSUYOSHI
IPC分类号： H04M3/26 , H04M3/22
摘要： PURPOSE:To avoid incorporating the test control function within the exchange device by installing the test device independently from the exchange device and then securing a connection between the exchange and test devices with the ordinary inter-exchange signal sequence and with the interface applied. CONSTITUTION:Test device 5-1 including test trunk 12-1 and control device 13-1 having the test control function is installed independently from exchange device 2-1. When the test is carried out, trunk 12-1 is connected to device 2-1 with the ordinary inter-exchange signal sequence plus the interface secured and via the channel. Thus device 2-1 regards device 5-1 as an independent station to perform the exchange process, at the same time carrying out the test of the exchange system via device 5-1.

7. 发明专利

JPS5758453A Regulating system 失效
标题翻译：调节系统
公开(公告)号：JPS5758453A
公开(公告)日：1982-04-08
申请号：JP13286180
申请日：1980-09-26
申请人： Fujitsu Ltd , Hitachi Ltd , Nec Corp , Nippon Telegr & Teleph Corp , Oki Electric Ind Co Ltd
发明人： YAMAMOTO YUUSUKE , KIN KATSUYOSHI , MANABE SHIROU , SUGI KUNITOSHI , SEIKE KENJI
IPC分类号： H04M3/22 , H04M3/36 , H04Q3/545
CPC分类号： H04M3/365
摘要： PURPOSE:To achieve a multiprocessor electronic exchange system which can perform economical, suitable confusing restriction, by providing a function to detect the remaining state of processed request in a communication device connected between an input and output processor and a call processor. CONSTITUTION:Processing request from input/output processors 2o-2i is sequentially stored in a storage circuit 31 in a communication device 30 to advance a count circuit 32. The stored processing request is transmitted to a call processor 40 sequentially and a count circuit 32 is subtracted by the transmission. If many processing requests come and the capability of the call processor 40 is exceeded, the index of the count circuit 32 is gradually increased. A discrimination circuit 33 sets a restriction display flip-flop, when the index of the circuit 32 reaches a prescribed number, and sets a restriction display flip-flop 34 and transmits a restriction signal to the processors 2o-2i to start the restricting operation of the line to an inputted load.
摘要翻译：目的：通过提供在连接在输入和输出处理器与呼叫处理器之间的通信设备中检测已处理请求的剩余状态的功能，实现可以执行经济，合适的混淆限制的多处理器电子交换系统。构成：来自输入/输出处理器2o-2i的处理请求被顺序地存储在通信设备30中的存储电路31中，以使计数电路32前进。所存储的处理请求被顺序发送到呼叫处理器40，并且计数电路32是通过传输减去。如果许多处理请求到来并且呼叫处理器40的能力被超过，则计数电路32的索引逐渐增加。鉴别电路33设置限制显示触发器，当电路32的索引达到规定数量时，设置限制显示触发器34，并向处理器2o-2i发送限制信号以开始限制操作到输入负载的行。

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