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1. 发明专利

JPH02246149A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR REMEDYING DEFECT THEREOF 失效
公开(公告)号：JPH02246149A
公开(公告)日：1990-10-01
申请号：JP6583989
申请日：1989-03-20
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI DEVICE ENG
发明人： SAKUTA TOSHIYUKI , ISHIHARA MASAMICHI , MIYAZAWA KAZUYUKI , HIROKI MASANORI , IWAI HIDETOSHI , NAKAMURA TAKASHI , TAKAHASHI YASUSHI , MAEDA TOSHIO , MATSUURA NOBUMI , HORI RYOICHI , SASAKI TOSHIO , SAKAI OSAMU , UCHIYAMA HIROYUKI
IPC分类号： G11C29/00 , G11C11/401 , G11C11/406 , G11C29/04 , H01L21/82 , H01L27/10
摘要： PURPOSE:To simplify and rationalize a layout by a method wherein a circuit having a RAM function is formed as a macrocell and a plurality of macrocells constitute a semiconductor storage circuit of a large storage capacity. CONSTITUTION:In this RAM, a plurality of memory blocks which has been formed as macrocells are arranged in a matrix manner. Sixteen memory blocks of about 4 Mbits each are arranged in four rows and four columns and have a large storage capacity of about 64 Mbits as a whole. One memory block constituted as the macrocell is provided with the following: a row-based address decoder which receives an address signal supplied through a timing/address generation circuit which have been made common; an address selection circuit composed of a word-line drive circuit, a column-based address decoder, a column selection-line drive circuit or the like; a timing generation circuit which generates a time-series timing pulse when an internal operation is required according to a memory array and an operating mode; a timing generation circuit for a selected memory cell; an input/output circuit which executes a write/readout operation of a data for the selected memory cell.

2. 发明专利

JPH07169288A BATCH ERASING TYPE NON-VOLATILE MEMORY 失效
公开(公告)号：JPH07169288A
公开(公告)日：1995-07-04
申请号：JP34193193
申请日：1993-12-13
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： NOZOE ATSUSHI , KOTANI HIROAKI , SAKAI OSAMU , TANAKA TOSHIHIRO , KUBOTA YASURO
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To increase operational speed and to improve using convenience by arranging required memory transistors(TR) in a matrix state at the intersection of a word line and a data line, erasing for each word line, and performing writing and reading through a latch circuit corresponding to a data line. CONSTITUTION:Memory cells of an insulation gate type FET having a structure of two layers gate are arranged at the intersection of word lines and data lines, and a memory array having memory cells of matrix arrangement is formed. And erasing operation is performed for each word line to which a control gate of a memory cell is connected. On the other hand, writing and reading operation are performed for each word line corresponding to data lines through a sense amplifier of a latch circuit used commonly as the write amplifier. Therefore, erasing, writing and reading of many bits for each word line are efficiently performed, memory access is performed at a high speed, interchangeability between a file memory and a magnetic memory device can be obtained and using convenience is improved.

3. 发明专利

JPH04186599A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH04186599A
公开(公告)日：1992-07-03
申请号：JP31395290
申请日：1990-11-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SASAKI TOSHIO , SHIMOHIGASHI KATSUHIRO , SAKAI OSAMU , KANNO TOSHIO , ETO TAKESHI , HORI RYOICHI , KAWAKAMI MASAMI
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04
摘要： PURPOSE:To read/write at a high speed by normally accessing a main memory, saving predetermined information becoming defective at the time of queuing in a spare memory, rewriting substitute bit information in the main memory normally at the time of returning, and further switching a defective input/output signal to the spare memory during accessing of the main memory. CONSTITUTION:No defective bit is in the cell of a memory block of a main memory 2 in a normal operation, and an access signal 120 is connected to an external access signal 110. For example, part of the cell of the memory 2 becomes a defective bit in a queuing state such as a refresh mode of a DRAM, etc. This location is previously stored in a memory 12 of a relief controller 6. The signal 120 is connected to an access signal 130 of a spare memory 4 in a queue conversion, information of the memory 2 is saved in the spare memory under the control of the defective memory 12 before it is normal, and the information of the memory 4 is similarly rewritten in the memory 2 in the case of normal conversion. With the configuration, the accessing time of the memory can be accelerated, saving or rewriting at the time of queuing is processed at a high speed.

4. 发明专利

JPH03194792A MEMORY MODULE 失效
公开(公告)号：JPH03194792A
公开(公告)日：1991-08-26
申请号：JP33576289
申请日：1989-12-25
申请人： HITACHI LTD
发明人： SAITO KAZUO , SUGANO TOSHIO , SAKAI OSAMU
IPC分类号： G11C29/00 , G11C11/401 , G11C29/04
摘要： PURPOSE:To easily obtain the convenience for use and the compatibility by providing an output selection control means which does not select read data from a storage area having a defect but selects read data from a storage area free from defects to give it to the external in accordance with the input level of a prescribed common external terminal. CONSTITUTION:In the write cycle, write data is given to all DRAMs M1 to M16; and in the read cycle, read data from a storage area free from defects out of data read out from all DRAMs M1 to M16 is selected and is given to external data input/output terminals DQ0 to DQ7. Consequently, defects of a part of memories M1 to M8 are compensated by the other memories M1 to M16 to have a 4-megabyte effective storage capacity. This control is performed by an output selection control circuit OSL. Thus, the same conve nience for use as a memory module using indefectible memores and the compati bility with it are easily obtained.

5. 发明专利

JPS59152589A Dynamic ram 失效
标题翻译：动态RAM
公开(公告)号：JPS59152589A
公开(公告)日：1984-08-31
申请号：JP2618083
申请日：1983-02-21
申请人： Hitachi Ltd
发明人： SAKAI OSAMU
IPC分类号： G11C11/401 , G11C11/34
CPC分类号： G11C11/34
摘要： PURPOSE:To extend a power source voltage margin, by precharging a dummy cell until a memory cell is set to the non-selected state after a sense amplifier is operated and forming stored information of the memory cell and a reference voltage with the same power source voltage. CONSTITUTION:A MOSFETQm is turned on to connect a capacitor Cs to a common data line DL, and a change of the potential of the data line DL which is generated in accordance with the electric charge quantity stored in the capacitor Cs is sensed, thus reading information. This change of the potential of the data line DL due to the electric charge quantity stored in the capacitor Cs appears as a very minute signal. A dummy cell DC is provided as a reference for detection of this minute signal. Even if a considerable variation (bump) is generated in a power source voltage Vcc in the time when a memory array is not selected, the memory cell and the dummy cell hold the storage level and the reference voltage level still in accordance with the power source voltage Vcc in the preceding operation state.
摘要翻译：目的：为了扩展电源电压裕度，通过预充电一个虚拟单元，直到在读出放大器工作之后将存储单元设置为非选择状态，并形成存储单元的存储信息和具有相同电源的参考电压电压。构成：MOSFETQm导通以将电容器Cs连接到公共数据线DL，并且感测根据存储在电容器Cs中的电荷量产生的数据线DL的电位的变化，从而读取信息。由于存储在电容器Cs中的电荷量导致的数据线DL的电位的这种变化看起来是非常微小的信号。提供虚拟单元DC作为用于检测该分钟信号的基准。即使在没有选择存储器阵列时的电源电压Vcc中产生相当大的变化（凸起），存储单元和虚设单元也保持与电源相关的存储电平和参考电压电平在前一操作状态下的电压Vcc。

6. 发明专利

JPS5850766A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS5850766A
公开(公告)日：1983-03-25
申请号：JP14790281
申请日：1981-09-21
申请人： HITACHI LTD
发明人： SAKAI OSAMU
IPC分类号： H01L21/822 , H01L27/02 , H01L27/04
摘要： PURPOSE:To supply the substrate voltage generating circuit with power constantly eliminating the photoetching process by a method wherein the substrate voltage generating circuit is contained in a semiconductor and the substrate is provided with the output through the intermediary of the diffused region other than the scribe region. CONSTITUTION:The metal wiring 7 extending from the substrate voltage gennerating circuit is formed on the periphery of semiconductor pellet surrounding the active region 15 to be connected to N type diffused layer 3. Another N type diffused layer 4 in the scribed region is formed around said N diffused layer 3 while the field oxide film 4 is formed between said diffused layers. Because the diffused layer 3 in the substrate voltage supply unit being electrically insulated from the diffused layer 2 in the scribe region by means of said field oxide film 4, the substrate may be supplied with the substrate voltage without fail under no influence of the irregularity of resistance as shown by the equivalent circuit 9.

7. 发明专利

JPS5825257A SEMICONDUCTOR IC DEVICE 失效
公开(公告)号：JPS5825257A
公开(公告)日：1983-02-15
申请号：JP12298681
申请日：1981-08-07
申请人： HITACHI LTD
发明人： SAKAI OSAMU
IPC分类号： H01L27/088 , H01L21/8234 , H01L27/02 , H01L29/78
摘要： PURPOSE:To improve the withstand degree of the electrostatic breakdown of IC of a drain-input type circuit by a method wherein a voltage applied between the gate and drain of a transmission gate MOSFET is restricted by providing another MOSFET between the gate and the earth potential. CONSTITUTION:A resistor R1 is connected to an input terminal 1, and MOSFET Q1 whose gate is connected to a reference potential terminal 2 is provided between the other end of the resistor and the terminal 2. One end of a transmission gate MOSFET Q2 is connected to a point of connection of the resistor R1 with FET Q1, while the other end thereof is connected to MOSFET Q4 arranged in an internal circuit. Moreover, MOSFET Q3 is put in a prescribed position in a prescribed manner. When a high voltage is impressed on an external earth potential terminal 2, the source potential of FET Q2 is made high through FET Q3, and even when an extraordinary high voltage is inputted in the drain-input type external terminal 1 under the above condition, the voltages between the drain and source of FET Q1 and Q3 become nearly equal to each other, and thus both MOSs are broken down simultaneously. Therefore, the breakdown voltage of FET Q2 is relaxed and the breakdown of the gate insulating film thererof is not prevented.

8. 发明专利

JPH09191074A MEMORY MODULE 失效
公开(公告)号：JPH09191074A
公开(公告)日：1997-07-22
申请号：JP1257297
申请日：1997-01-27
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： KANNO TOSHIO , TSUKUI SEIICHIRO , SAKAI OSAMU
IPC分类号： H05K1/11 , G11C5/00 , H01L25/04 , H01L25/10 , H01L25/18 , H05K1/00 , H05K1/18
摘要： PROBLEM TO BE SOLVED: To meet the requirements of design specification changes of a memory module flexibly by a method wherein terminal electrodes are so arranged as to be able to change functions in accordance with the connection states of SMT-type conducting units with which the terminal electrodes of memories and outer terminals are electrically connected to each other. SOLUTION: One jumper chip 4 is mounted between a land 12c and a land 12d with solder so as to correspond to a memory module with an access time of 85ns. Two jumper chips 4 are mounted to make lands 12a and 12b and lands 12c and 12d electrically continuous with each other so as to correspond to a memory module with an access time of 100ns. No jumper chip 4 is mounted and both module terminals 5a and 5b are NC so as to correspond to a module with an access time of 120ns. With this constitution, the manufacturing lead time of a memory module can be shortened significantly and, further, the design cost, the manufacturing cost, etc., can be reduced and an economical memory module can be obtained.

9. 发明专利

JPH0142141B2 失效
公开(公告)号：JPH0142141B2
公开(公告)日：1989-09-11
申请号：JP3040680
申请日：1980-03-12
申请人： HITACHI LTD
发明人： SAKAI OSAMU
IPC分类号： H01L27/04 , G05F3/20 , H01L21/822 , H01L29/78

10. 发明专利

JPS6260194A DYNAMIC RAM 失效
公开(公告)号：JPS6260194A
公开(公告)日：1987-03-16
申请号：JP19942085
申请日：1985-09-11
申请人： HITACHI LTD
发明人： MISHIMA MICHIHIRO , SAKAI OSAMU
IPC分类号： G11C11/408 , G11C11/34
摘要： PURPOSE:To improve the mass producitivity of dynamic RAM of different address supply systems by using some of row address signals supplied by a multi-address system as column address signals. CONSTITUTION:Addresses supplied from external terminals A0-A7 are turned into internal row addresses via row address buffers X1-X7. While the internal address supplied via a row address buffers XO is turned into an internal column address. Then the addresses supplied from terminals A1-A6 are supplied to a column address decoder C(Y)-DCR together with the internal column addresses processed by column address buffers Y1-Y6. Thus it is not needed to change a memory array, address decoder, etc. into each corresponding constitution even in case the address signals have different numbers of bits. This improves the mass productivity of dynamic RAM of different multi-address supply systems.

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