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1. 发明专利

JPH10199910A SEMICONDUCTOR DEVICE, MANUFACTURE THEREOF AND IC CARD USING THE SAME 失效
公开(公告)号：JPH10199910A
公开(公告)日：1998-07-31
申请号：JP25000197
申请日：1997-08-28
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： NAKAJIMA KOICHI , ARAI NORINAGA , UEHARA KAZUAKI , NAKAJO TAKUYA , TAKESHITA KAZUYUKI , ENDO TSUNEO , SATO TSUNEO
IPC分类号： B42D15/10 , G06K19/077 , H01L21/56 , H01L21/60 , H01L23/28
摘要： PROBLEM TO BE SOLVED: To provide a flexible COB(chip-on-board package) IC having a specified strength for flexible IC cards. SOLUTION: A flexible COB/IC 10 having a specified strength for IC cards is composed of a carrier 12 and a chip 21. The carrier 12 is an insulating flexible sheets 15 having eight outer side leads at both sides of a center outer lead 16a on one main surface, with connection holes 18 bored at positions facing side outer leads 16. The chip 21 is disposed in a hole 17 at the center of the sheet 15 and fixed to the center outer lead 16a, through an insulative adhesive layer 24. Wires 26 bonded to electrode pads 22 of the chip 21 are connected to respective side outer leads 16 at the connection holes 18. The chip 21 and wires 26 on the sheet 15 are sealed with a resin, to form a resin sealed body 28 having a convex part 29 at the top surface.

2. 发明专利

JPH03132183A DIGITAL IMAGE REPRODUCING SYSTEM 失效
公开(公告)号：JPH03132183A
公开(公告)日：1991-06-05
申请号：JP26890589
申请日：1989-10-18
申请人： HITACHI LTD
发明人： TAKESHITA KAZUYUKI , NAKANO KENJI
IPC分类号： H04N5/92 , G11B20/10 , G11B27/00 , G11B27/30 , H04N5/937
摘要： PURPOSE:To perform slow reproduction without generating bleeding in an image by writing only a signal without an error from a magnetic tape on a frame memory, and selectively holding the signal of a frame or a field in which the update of the storage area of the frame memory is completed. CONSTITUTION:A means 9 to perform the identification of the field or the frame to which data in a reproducing signal belongs is provided, and a first memory 6 is equipped with a means 8 to prohibit write corresponding to the error of the reproducing signal, and a second memory 12 capable of specifying a write period is provided, and the second memory 12 is connected to the rear stage of the first memory 6. A means to detect the completion of the update of the specific field or frame of the first memory 6 is provided, and only the signal whose update is completed is selectively written with a detecting means. In such a way, since the write, holding, and the write are repeated in the above sequence, the image can be outputted as a field frame feed image to an output terminal 15, and a field slow image without generating the bleeding can be obtained.

3. 发明专利

JPH01240086A PICTURE SIGNAL MODIFYING SYSTEM 失效
公开(公告)号：JPH01240086A
公开(公告)日：1989-09-25
申请号：JP6570688
申请日：1988-03-22
申请人： HITACHI LTD
发明人： TAKESHITA KAZUYUKI
IPC分类号： H04N5/92 , G06T5/20 , G11B20/18
摘要： PURPOSE:To obtain the most natural substitute signal even in the suddenly changing part of a picture by preparing an (n) number of digital filters as signal restoring means, making the coefficients of necessary digital filters zero concerning picture elements in which errors occur and multiplying the result of an operation by a correction factor. CONSTITUTION:When an error flag 2 is hoisted, picture elements become zero, are added to multipliers 21 by switches 13-20, multiplied by respective coefficients and sum 23 is operated by an adder 22. On the other hand, the error flags in taps are added to a control ROM 24, error distribution is examined, a correction factor 25 is outputted and added to a correcting multiplier 26. An output 27 of the multiplier 26 is the substitute composite signal and when the error flag is not hoisted in a Y10, the Y10 is selected and outputted by a switch 28.

4. 发明专利

JPH01213875A SYSTEM FOR DETECTING AND CORRECTING SKEW QUANTITY 失效
公开(公告)号：JPH01213875A
公开(公告)日：1989-08-28
申请号：JP3755988
申请日：1988-02-22
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： OKIGUCHI KOTARO , UMEMOTO MASUO , KANEKO AKIRA , AIHARA TOSHIHARU , TAKESHITA KAZUYUKI
IPC分类号： G11B20/20
摘要： PURPOSE:To easily detect and correct skew quantity by counting a time to regenerate a synchronizing signal or an identification signal from a recording medium and comparing the time with reference time. CONSTITUTION:A video to be recorded by video heads 3, 4-6 of a rotary drum 2 is taken out in order by a video head switching circuit 29 and conducted through ID signal detecting circuits 30 and 31 and a synchronizing signal detecting circuit 32 to a gate generating circuit 38. When a gate signal phi9 of the circuit 38 is 'H', a clock phi10 of a frequency divider 28 is counted by a programmable counter 40. A time length t2 between counted synchronizing signals S2 and Sm at the time of regenerating is fetched into a RAM 23 and a time length t1 between the computed signals S2 and Sm is integrated to a ROM 24. Then, a program is included to calculate a differential time DELTAt1=t1-t2. On the other hand, a CPU 22 executes the program of the ROM 24 and calculates the skew quantity error DELTAt1 and tension to obtain DELTAt1=0 is calculated from the program of the ROM 24. Then, tension setting 42 is executed and the skew quantity is detected and corrected.

5. 发明专利

JPS62188446A SYNCHRONIZING DETECTION CIRCUIT 失效
公开(公告)号：JPS62188446A
公开(公告)日：1987-08-18
申请号：JP2882886
申请日：1986-02-14
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： ETO YOSHIZUMI , TAKESHITA KAZUYUKI , KANEDA HIDEHIRO , UMEMOTO MASUO
IPC分类号： H04N1/36 , G11B20/10 , G11B27/30 , H04J3/06 , H04L7/08
摘要： PURPOSE:To detect a synchronizing pattern at the operation speed lower than the code speed by dividing a reception code series into n-set of code series to decrease the operation speed into 1/n and modifying the original synchronising pattern into any of n-kind depending of the divided phase. CONSTITUTION:A reception code series and its clock are given to input terminals 1, 2. The clock is converted into a 1/4 frequency by a counter 3. And a 4-bit serial/parallel converter 4 outputs the code series 1 to 1-D at every 4-bit at the same time. Delay elements 5-7 use the output clock of the counter 3 to retard the outputs B-D of the serial/parallel converter 4 by a time corresponding to one clock. Synchronizing pattern detection circuits 8-11 deciding whether or not the phase of ai-di (i=1-4) exists are provided to the input. Since the synchronizing pattern is detected without fail by the detection circuit, an OR circuit 12 obtains the OR of outputs of the detection circuits 8-11, then a synchronizing signal is obtained at an output terminal 13. Thus, the synchronizing pattern included in the reception code series is detected at the operation speed lower then the code speed.

6. 发明专利

JPS62171287A DIGITAL PICTURE RECORDING AND REPRODUCING DEVICE 失效
公开(公告)号：JPS62171287A
公开(公告)日：1987-07-28
申请号：JP1195586
申请日：1986-01-24
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： ETO YOSHIZUMI , UMEMOTO MASUO , TAKESHITA KAZUYUKI , OKIGUCHI KOTARO
IPC分类号： H04N5/7826 , H04N5/782 , H04N5/92
摘要： PURPOSE:To prevent mis-detection of a synchronizing code by recording a television signal subject to digital coding so as to arrange a synchronizing code block in adjacent tracks with an equal azimuth angle so as to forecast the detection time of the next synchronizing code. CONSTITUTION:An error correction (or detection) code P is added to a picture data D obtained from a television signal in a digital VTR. Further, the signals D, P are collected, an address A of a synchronizing code S is added and the result is used as one synchronizing block. The synchronizing code S has a pattern detected by a reproducing code and the location of the address A in the code, the data D and the section of the correction code P are confirmed by using the pattern. In this invention, the synchronizing blocks 2 are arranged between adjacent tracks on a tape 1. When the synchronizing code blocks are arranged between the adjacent tracks, the tape speed differs at the recording and reproduction and even when the head reproduces a signal while bridging over plural tracks at the reproduction, the reproduced synchronizing codes form a prescribed interval. AS a result, the detection of the synchronizing code is operated effectively.

7. 发明专利

JPS59221812A CODE PROCESSING CIRCUIT 失效
公开(公告)号：JPS59221812A
公开(公告)日：1984-12-13
申请号：JP9565583
申请日：1983-06-01
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： TAKESHITA KAZUYUKI , HIRANO YASUHIRO
IPC分类号： G11B20/18 , H03M13/00 , H03M13/27 , G11B5/09 , H03K13/32
摘要： PURPOSE:To detect an error part by detecting an error correcting part by an error detecting means, because a different pattern is applied to data whose time has been corrected, in case when a malfunction for correcting a time base is generated. CONSTITUTION:When a time base correction is erroneous, for instance,a line of blocks 19-27 is written in a line of blocks 10-18 by mistake. In this case, as for a parity 27, a code sequence of only the latter half 4 bits is generated, when an inversion of data is 8 bits. On the other hand, as for a parity 18, when an inversion of the data is 8-bit, a code sequence of only the first half 4 bits is generated. Since writing has been executed in the blocks 10-18 by mistake, as for the data of the blocks 19-26, a parity inspection is executed from the inverted one of the first half 4 bits, and as a result, a code error can be dcided. In this way, even if an error of a time base correction is generated at the time of reproducing, an error part can be detected without fail, and in this regard, an addition of hardware required for said purpose is very small.

8. 发明专利

JPS5949088A Reproducer of digital video signal 失效
标题翻译：数字视频信号再现器
公开(公告)号：JPS5949088A
公开(公告)日：1984-03-21
申请号：JP15809582
申请日：1982-09-13
申请人： Hitachi Denshi Ltd , Hitachi Ltd
发明人： HIRANO YASUHIRO , TAKESHITA KAZUYUKI
IPC分类号： H04N9/804 , H04N9/808 , H04N9/87
CPC分类号： H04N9/87
摘要： PURPOSE:To reproduce a normal color picture with less deterioration for any video signal having different fields on the way of one line, by performing a chromatic inversion to an input added with redundant data so as to reserve the continuity of a color subcarrier phase. CONSTITUTION:An input video signal of A, B, C channels is given to a point (p) in the variable speed reproduction of a digital VTR recorded in three channels. A redundant data adding circuit 1 forms a signal at a point (q) where the redundant data is added to the last of a video signal A of the beginning of a video signal C, and a signal at a point (r) where the redundant data is added to the beginning and end of a video signal B. Further, the redundant data is produced so that the phase of the color subcarrier is continuous. These data are inputs to chromatic inverters 2, 3. Then, a switch 4 selects an output of the two chromatic inverter and obtains a signal at a point (s) where the chromatic inversion is attained. On the other hand, a signal at a point (t) delayed at a delay circuit 5 is selected by a switch 6 and a video signal at a point (u) is obtained, where the phase of color subcarrier is continuous.
摘要翻译：目的：通过对添加有冗余数据的输入进行色反转，以便保留彩色副载波相位的连续性，再现具有在一行途中具有不同场的任何视频信号的恶化的正常彩色图像。构成：记录在三个通道中的数字VTR的可变速度再现中给予A，B，C通道的输入视频信号到点（p）。冗余数据添加电路1在（q）点处形成信号，其中将冗余数据添加到视频信号C的开头的视频信号A的最后一个，以及在（r）处的信号，其中冗余数据被添加到视频信号B的开始和结束。此外，产生冗余数据，使得彩色副载波的相位是连续的。这些数据是彩色反相器2,3的输入。然后，开关4选择两个彩色反相器的输出，并获得在获得色反转的点处的信号。另一方面，通过开关6选择在延迟电路5处延迟的点（t）处的信号，并且获得在点（u）处的视频信号，其中彩色副载波的相位是连续的。

9. 发明专利

JPH0336887A DIGITAL PICTURE REPRODUCTION SYSTEM 失效
公开(公告)号：JPH0336887A
公开(公告)日：1991-02-18
申请号：JP16997989
申请日：1989-07-03
申请人： HITACHI LTD
发明人： TAKESHITA KAZUYUKI , NAKANO KENJI
IPC分类号： H04N5/92 , G06T1/00 , H04N5/783 , H04N5/926 , H04N5/937 , H04N5/945
摘要： PURPOSE:To prevent blur of a picture at slow reproduction by identifying a field or a frame with a reproduction signal belonging thereto when a magnetic tape is driven at a different speed from that at recording and writing only a reproduction signal selected into a designated area. CONSTITUTION:A digital picture signal is recorded on a magnetic tape so as to one field period covers n-set of tracks, a reproduction signal S from the magnetic tape driven at a different speed from that at recording is fed to an input terminal 1 and a field ID separated from the reproduction signal S is inputted to the input terminal 3. A field identification circuit 9 discriminates to which of fields 0, 1 a block inputted from the input terminal 1 belongs and the field selected by a write control counter 11 is written in a frame memory 6 of an address designated by a write address generator 7. Thus, the blur of a reproduced picture when the frame memory 6 is read simultaneously is prevented.

10. 发明专利

JPS6489678A SIGNAL PROCESSING SYSTEM 失效
公开(公告)号：JPS6489678A
公开(公告)日：1989-04-04
申请号：JP24370387
申请日：1987-09-30
申请人： HITACHI LTD
发明人： TAKESHITA KAZUYUKI
IPC分类号： H04N5/92 , G11B15/18 , G11B20/10 , G11B27/00 , G11B27/30
摘要： PURPOSE:To effectively use a head output without rejecting it by using a common address and in addition writing data in the different address for every channel when the signals of n-channels are time-division processed and written in the memories of m-systems. CONSTITUTION:The signals 1a-1c of the respective channels reproduced from a head are inputted to a parallel memory circuit 4 through a cross conversion circuit 2. The memory circuit 4 is provided with the memories of m-systems, and the memories of m-systems are written/read by the common address 8 from an address generation circuit, and in addition, data is written/read in/from the address different for every channel. The read out data is outputted through the cross conversion circuit 6.

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