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1. 发明专利

JPH02187850A BUS ARBITRATION SYSTEM 失效
公开(公告)号：JPH02187850A
公开(公告)日：1990-07-24
申请号：JP714589
申请日：1989-01-13
申请人： HITACHI LTD , SAKAMURA TAKESHI , HITACHI MICROCUMPUTER ENG
发明人： SAKAMURA TAKESHI , NAKAGAWA TAKAAKI , TAKANO MAKOTO , MIYASHITA KOICHI
IPC分类号： G06F13/374 , G06F15/16 , G06F15/177
摘要： PURPOSE:To improve the activity ratio of a bus by deciding and storing bus use sequence successively according to priority, and performing the delivery of the right of using of a bus according to stored bus use sequence. CONSTITUTION:A microcomputer system on which a bus arbitration system is applied is constituted of plural modules. In the module A, a priority level number generation circuit BNG which realizes a bus arbitration function on a microprocessor CPU that is the center of control, a priority comparator BCP, and an arbitration control circuit ABC are provided, and it decides the bus use sequence successively according to the priority allocated to the request of the use of the bus, respectively, and stores respective bus use sequence in a bus master sequence storage circuit MRG. And by performing the delivery of the right of using of the bus among the modules according to the stored bus use sequence, the activity ratio of the bus can be improved.

2. 发明专利

JPH02280262A BUS ACCESS SYSTEM AND BUS SYSTEM 失效
公开(公告)号：JPH02280262A
公开(公告)日：1990-11-16
申请号：JP10219989
申请日：1989-04-20
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG , SAKAMURA TAKESHI
发明人： SAKAMURA TAKESHI , TAKANO MAKOTO , NAKAGAWA TAKAAKI , MIYASHITA KOICHI , HAGINO KEIKO
IPC分类号： G06F13/38
摘要： PURPOSE:To constitute a system by using devices with different bus specification by defining the system by a state signal transmitted via a prescribed signal line on a bus without fixing the role of each signal line comprising the bus. CONSTITUTION:The state signals representing the bus specification are outputted from bus masters MPU1 and 2 using the bus BUS, and input/output devices I/01-4 on the bus BUS which is used as slaves monitor the signal, and validates an input/output signal only when the bus masters are provided with the same bus specification. Therefore, no collision or contention occurs in the signal even when plural bus masters MPU1 and 2 with different bus specification and the input/output devices I/01-4 are mixed in the same bus BUS. Thereby, it is possible to constitute the system by using the devices with different bus specification, and to easily change an address or data width, etc., and to improve the flexibility and extendability of the system using the bus BUS.

3. 发明专利

JPH02116947A DATA TRANSFER SYSTEM 失效
公开(公告)号：JPH02116947A
公开(公告)日：1990-05-01
申请号：JP27145788
申请日：1988-10-26
申请人： SAKAMURA TAKESHI , HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： SAKAMURA TAKESHI , HAGINO KEIKO , MIYASHITA KOICHI , TAKANO MAKOTO , NAKAGAWA TAKAAKI
IPC分类号： G06F13/42 , G06F13/36
摘要： PURPOSE:To execute the data transfer at a high speed by bringing a response of a data strobe signal and an acknowledge signal to handshake in every other bus cycle. CONSTITUTION:At the time of start of a block data transfer, a device of a master side outputs a head address of block data onto a bus, and a device of a slave side latches the head address and informs a start of a bus cycle. Thereafter, by bringing automatically the address to increment, whenever a data strobe signal DS is varied, a destination address is obtained.

4. 发明专利

JPH03276247A INTERRUPTION CONTROL CIRCUIT 失效
公开(公告)号：JPH03276247A
公开(公告)日：1991-12-06
申请号：JP7333490
申请日：1990-03-26
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： MOCHIZUKI ISAMU , MIYASHITA KOICHI
IPC分类号： G06F13/24 , G06F9/46 , G06F9/48
摘要： PURPOSE:To evade a deadlock state in the interruption processing of an edge sense system by securing a constitution where the interruption signal set to an interruption handler is once negated at the end of an acknowledge cycle produced from the interruption handler and then asserted again after a prescribed time. CONSTITUTION:The function modules 20 and 30 are provided with the interrupters 2 and 3 serving as the interruption generation control circuits which produce the interruption signals IRQ to an interruption handler 1. Both interrupters 2 and 3 own the functions to decide the interruption acknowledge cycles produced from the handler 1. Furthermore a function is added to once negate the signal IRQ to the handler 1 at the end of the interruption acknowledge cycle and then asserts the signal IRQ again after a prescribed time. In such a constitution, a deadlock state is evaded in the interruption processing of an edge sense system.

5. 发明专利

JPH03138744A DATA TRANSMISSION METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH03138744A
公开(公告)日：1991-06-13
申请号：JP27583889
申请日：1989-10-25
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： NAKAGAWA TAKAAKI , MIYASHITA KOICHI
IPC分类号： G06F11/14 , G06F13/00
摘要： PURPOSE:To continue data transfer in a series of data transfer operations by inverting the logic of data to transfer data at the time of occurring data transfer error due to trouble of a data transmission system. CONSTITUTION:In the case of occurrence of data transfer error due to trouble of the data transmission system including a data bus 13, the logic of transmission data is inverted in a single chip microcomputer 1 or a memory device 7 as the data transmission side. Thus logic inverted data is put on the data bus 13, and the logic of data on the data bus 13 is inverted again to restore the original logic in the memory device 7 or the single chip microcomputer 1 as the reception side. Consequently, data is normally transmitted to the data transmission side regardless of trouble of the data transmission system. Thus, data transfer is continued regardless of the occurrence of data transfer error.

6. 发明专利

JPH03102447A DATA PROCESSING SYSTEM 失效
公开(公告)号：JPH03102447A
公开(公告)日：1991-04-26
申请号：JP24002989
申请日：1989-09-18
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： NAKAGAWA TAKAAKI , MIYASHITA KOICHI
IPC分类号： G06F13/00
摘要： PURPOSE:To easily set an optimum bus time-out period by deciding this time-out period based on the bus time-out period information on all slaves. CONSTITUTION:A bus time-out detecting circuit 6 has a function to decide an optimum bus time-out period of a data processing system based on the time- out period information BTOUT1* - BTOUT3* on all slaves, i.e., a peripheral circuit 5 and an input/output device 10. The circuit 6 also has another function to assert a bus error signal BERR at a low level if no answer is received from the slave within the optimum bus time-out period. Then the longest bus time-out period out of those of the slaves is defined as an optimum bus time-out period. Thus the optimum bus time-out period is easily set in a data processing system.

7. 发明专利

JPH01134652A DATA PROCESSING SYSTEM 失效
公开(公告)号：JPH01134652A
公开(公告)日：1989-05-26
申请号：JP29211387
申请日：1987-11-20
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： OKAWA TOMOYUKI , MIYASHITA KOICHI
IPC分类号： G11C11/406 , G06F13/20 , G06F13/36 , G11C11/34
摘要： PURPOSE:To prevent the refresh leaking of the D-RAM of a common resource by switching the bus of a bidirectional accessible resource when an access execution period timed result obtained with a timer exceeds a normal time. CONSTITUTION:While a timer 7 is activated by a switching signal SEL 2 from a bus switching control circuit 6 according to an access request REQ 2 from a system bus 3c side, a gate 4b is opened, and a D-RAM 2 of a resource memory is connected with a bus 3c. When the timed result of the timer 7 exceeds a normal refresh cycle, the gate 4b is closed with a signal REL from the timer 7 through the circuit 6, a gate 4a is opened, and the access right of a memory 2 is automatically switched to an MPO 1 side forcibly. Thus, a refresh by a built-in refresh control circuit can be surely executed, and a data vanishing due to the refresh leaking can be prevented.

8. 发明专利

JPH01217521A INTERRUPTION CONTROL CIRCUIT 失效
公开(公告)号：JPH01217521A
公开(公告)日：1989-08-31
申请号：JP4206288
申请日：1988-02-26
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： MOCHIZUKI ISAMU , MIYASHITA KOICHI
IPC分类号： G06F9/48 , G06F9/46
摘要： PURPOSE:To surely distinguish interruption which is continuously generated, starting a correspondent interruption processing and to evade from falling into a dead-lock condition by providing an interruption generation control part, etc., to have an interruption end detecting part and a delay circuit. CONSTITUTION:An interruption end detecting part 2 detects the change from the low level to high level of interruption requesting signal inversions IRQ 1-IRQn from an interrupting request input part 1 and sends a mask signal inversion MASK to an interruption generation control part 3. The control part 3 inputs a mask signal from the detecting part 2 and a receiving signal from the input part 1 and generates an interruption requesting signal inversion IRQ to the interruption handler of a microprocessor. A delay circuit DLY of the control part 3 to be operated by a system clock gurantees a minimum time from the detection of a interruption processing end to the edge reception of the next interrupting request. Thus, the interruption, which is continuously generated, is distinguished without fail and the correspondent interruption processing is started. Then, a system can be evaded from falling into the dead- lock condition.

9. 发明专利

JPS63200247A MEMORY DEVICE 失效
公开(公告)号：JPS63200247A
公开(公告)日：1988-08-18
申请号：JP3144887
申请日：1987-02-16
申请人： HITACHI LTD
发明人： KAWACHI MITSUYUKI , MIYASHITA KOICHI
IPC分类号： G06F12/08 , G06F12/00 , G06F12/06
摘要： PURPOSE:To obtain a large-capacity memory having a high working speed by using a main memory having a comparatively low working seed and an auxiliary memory having a comparatively high working seed or a data buffer to constitute an information memory part and storing and reading out the addresses corresponding to the data on the auxiliary memory and the data buffer respectively. CONSTITUTION:The main memories MM0-MM3 consists of the dynamic RAM together with an auxiliary memory HSM consisting of a static RAM and a data buffer FF consisting of a TTL circuit respectively. A memory circuit of a control part CONT stores the addresses corresponding to the data stored in the buffer FF and the memory HSM respectively. In a reading state the reading addresses are collated with those stored addresses and the same addresses if detected and read out of the buffer FF. Then the data coincident with the address of the HSM is transferred to the buffer FF and read out. While the different addresses are outputted from those memories MM0-MM3 via the buffer FF and written into the HSM to be fetched by the memory circuit.

10. 发明专利

JPH0212957A ELECTRONIC APPARATUS 失效
公开(公告)号：JPH0212957A
公开(公告)日：1990-01-17
申请号：JP16444288
申请日：1988-06-30
申请人： HITACHI LTD , HITACHI YONEZAWA DENSHI KK
发明人： MIYASHITA KOICHI , OHASHI AKIRA
IPC分类号： H01L23/538 , H05K1/02 , H05K1/18
摘要： PURPOSE:To prevent an electronic apparatus from erroneously operating and to improve electric reliability by providing first wirings linearly, and second wirings nonlinearly or smaller in width or thickness of the wirings than that of the first wirings in the apparatus which places a ZIP type semiconductor device. CONSTITUTION:A ZIP type semiconductor memory 2 connected to wirings 3, 4 is placed on an intersection between wirings 3 and 4 extending in different directions on a printed circuit board 1. The wirings 3 extending in columnar direction are composed linearly, and the wirings 4 extending in row direction are composed nonlinearly. Accordingly, the difference between the characteristic impedances of the transmission lines of the wirings 3 and 4 upon specific shape of the memory 2 is reduced, and the difference of voltage reflection coefficients of both is decreased. Thus, the phase difference of the signals to be transmitted to the wirings 3, 4 is reduced, thereby preventing the writing or reading of information from erroneously operating.

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