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1. 发明专利

JPH04196810A DIFFERENTIAL PULSE WIDTH RESTORATION CIRCUIT 失效
公开(公告)号：JPH04196810A
公开(公告)日：1992-07-16
申请号：JP32316290
申请日：1990-11-28
申请人： HITACHI LTD , HITACHI COMPUTER ENG
发明人： MATSUMOTO TAKASHI , IWATA HIDENOBU
IPC分类号： H03K5/04 , H03K3/02
摘要： PURPOSE:To allow any input pulse to have the same pulse width by connecting the output of a differential amplifier with the reset terminal of a differential R-S flip flop, and making the delay time of the differential amplifier to be longer than that of the differential amplifier of a differential differentiation circuit. CONSTITUTION:Inputs C and D are connected with the A and A' of a differential amplifier circuit 2, and a differential amplifier 1. The inputs C and D passing through the amplifier 1 are turned into E and F after delayed by an X time, and respectively inverted and connected with the B' and B. The outputs G and H of the circuit 2 are obtained after differentiating the C and D. This circuit 2 is used as the differential differentiation circuit, the outputs G and H are connected with the S and S' of a differential R-S flip flop 4, and the rising time of outputs L and M is decided. Moreover, the outputs L and M of the flip 4 are connected with a differential amplifier 3, delayed by only a Y time longer than the X time, the outputs J and K of the amplifier 3 are connected with the R and R' of the flip 4, the outputs L and M of the flip 4 are reset, and the rising time of the pulse is decided. Thus, the pulses of the outputs L and M having the always constant pulse width for the Y time can be obtained.

2. 发明专利

JPH05223898A IC TESTER 失效
公开(公告)号：JPH05223898A
公开(公告)日：1993-09-03
申请号：JP2510492
申请日：1992-02-12
申请人： HITACHI LTD , HITACHI COMPUTER ENG
发明人： IWATA HIDENOBU , MATSUMOTO TAKASHI , ISHIMARU HIROYUKI
IPC分类号： G01R31/28 , G01R31/3183
摘要： PURPOSE:To accomplish data delay processing for the speed of an element, exceeding its operating speed. CONSTITUTION:The test data string of data rate (x) is emitted by IC tester 2 ALPG 21 to an LSI 1 and a correction latch circuit 24. The correction latch circuit 24 separates the test data string by a separatorapart and distributes to four systems of delay circuits. Each system of delay circuit delays the partial test data string, which was separated and whose data rate has become x/4, by the use of operation clocks and passes it to a multifold part. The multifold part time divides the outputs of the four systems of delay circuits and turns them multifold, restores the test data of the data rate (x), and passes it to a comparator circuit 25. The comparator circuit 25 compares this with the output data from the LSI and outputs a judgement.

3. 发明专利

JPH06243188A DELAY TIME CORRECTING SYSTEM 失效
公开(公告)号：JPH06243188A
公开(公告)日：1994-09-02
申请号：JP2560893
申请日：1993-02-15
申请人： HITACHI LTD , HITACHI COMPUTER ENG
发明人： IWATA HIDENOBU , MATSUMOTO TAKASHI , YOSHINO RYOZO , HIYAMA TORU , KAWASHIMA MASATOSHI
IPC分类号： G06F17/50 , G06F15/60
摘要： PURPOSE:To correct a path delay time after the end of layout and wiring of cells without changing already prepared wiring information at the time of LSI design. CONSTITUTION:Delay time correcting circuits DLY0 to DLY3 resolve the delay time differences brought about by inter-cell wiring length between FFs FF0 to FF3 and FFs FF4 to FF7. If it is necessary to correct the delay times of DLY0 to DLY3 after the end of layout and wiring of cells at the time of LSI design, cells for delay time correction which are preliminarily prepared and have the same size and pin arrangement as circuits DLY0 to DLY3 and are different by delay times are substituted for circuits DLY0 to DLY3 to correct the delay times.

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