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1. 发明专利

JP2002092055A METHOD FOR DESIGNING LOGIC CIRCUIT, SYSTEM FOR SUPPORTING DESIGN OF LOGIC CIRCUIT AND COMPUTER READABLE RECORDING MEDIUM 失效
公开(公告)号：JP2002092055A
公开(公告)日：2002-03-29
申请号：JP2000279734
申请日：2000-09-14
申请人： HITACHI LTD
发明人： MIYAZAKI HIROSHI , EGUCHI KAZUHIKO , TANIMOTO MASAAKI
IPC分类号： G06F9/06 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To shorten a time by optimizing logic synthesis for logic circuit description in a hardware description language. SOLUTION: The optimization algorithm candidates of a plurality of circuit blocks given in logic circuit description in the hardware description language are decided by considering the humming distances of the circuit blocks (S1-S3). Then, the circuit blocks in which the optimization algorithm candidates decided by the first processing are made common are grouped by considering the level of connection of the circuit blocks (S4-S6). The result of the grouping is obtained for the circuit blocks whose characteristics are clear in terms of the algorithm candidates or the level of connection, and there are remaining circuit blocks whose characteristics are unclear. Then, the result of the grouping is reflected on the initial state, and the grouping of the plurality of circuit blocks is optimized by a genetic algorithm so that the optimization of the grouping of the circuit blocks whose characteristics are unclear can be promoted (S7-S13).

2. 发明专利

JPH10336004A SEMICONDUCTOR INTEGRATED CIRCUIT AND DATA PROCESSING SYSTEM 失效
公开(公告)号：JPH10336004A
公开(公告)日：1998-12-18
申请号：JP14645497
申请日：1997-06-04
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： TANIMOTO MASAAKI , TAKEDA TAKAHIDE , YAMAGISHI KAZUSHIGE , KIKUCHI AKIRA
IPC分类号： H03K19/0175
摘要： PROBLEM TO BE SOLVED: To enable the amplitude of the interface signal with the outside of a semiconductor integrated circuit using a single power source to select both a voltage which is nearly equal to a power supply voltage and a lower voltage. SOLUTION: A logic circuit 16 selects either a current route Vdd, MP27, MP2, and 13 through which a high-level output voltage which is nearly equal to an external power supply voltage Vdd is supplied to an external signal terminal PDi or another current route Vdd, MP6, MN2, and 13 through which a high-level output voltage which is lower than the external power supply voltage Vdd is supplied to the signal terminal PDi in accordance with the state of a mode signal MODE. The on-resistance or mutual conductances of the current routes are made different from each other so that the output voltage levels of the routes may become different from each other without making any through current to flow.

3. 发明专利

JP2003216683A FUNCTION VERIFICATION UNIT 审中-公开
公开(公告)号：JP2003216683A
公开(公告)日：2003-07-31
申请号：JP2002011953
申请日：2002-01-21
申请人： HITACHI LTD
发明人： TANIMOTO MASAAKI , ARA HIROMI , SUZUKI TAKASHI , ITO MASAKI , UCHIBE KONAGI
IPC分类号： G06F17/50
摘要： PROBLEM TO BE SOLVED: To provide a function verification generation unit capable of preparing the function verification description to verify function verification items of a circuit to be verified even when a person in charge of verification does not learn HDL or a verification description language other than HDL, a designer who has learned HDL does not learn the verification description language other than HDL, or the function verification description itself described in HDL is not verified, and a description method in which a designer or a person in charge of verification clearly and uniformly describes the verification content of the circuit operation by using a timing diagram. SOLUTION: The function verification description generation unit having a means to input the logical relationship between wave profiles and the generation information of the logical relationship in the timing diameter and a means to generate the verification description from the timing diagram based on the logical relationship between the wave profiles and the generation information of the logical relationship comprises a terminal information extracting unit 1, a timing diagram editing unit 2, a verified operation extracting unit 3, and a verification description generation unit 4. COPYRIGHT: (C)2003,JPO

4. 发明专利

JP2000268080A STATIC/DYNAMIC TIMING INSPECTING METHOD AND STORING MEDIUM 失效
公开(公告)号：JP2000268080A
公开(公告)日：2000-09-29
申请号：JP9055899
申请日：1999-03-31
申请人： HITACHI LTD
发明人： TANIMOTO MASAAKI
IPC分类号： G01R31/28 , G06F9/45 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To efficiently execute reliable timing inspection by identifying a counter means in an object circuit and identifying clock information in the object circuit based on information of the identified counter means in static/dynamic timing inspection dividing processing. SOLUTION: The clock information extracting part 11 of a static/dynamic timing inspection dividing part 6 recognizes a clock generation circuit being a counter means consisting of an optional counter in an object circuit, identifies the waveform of a clock generated inside of the generation circuit and outputs object circuit information with clock information and asynchronous flip-flop/ asynchronous latch information to a circuit restriction inspecting part 12. The part 12 defines the clock waveform and outputs asynchronous clock waveform information to a dynamic timing inspection applying part recognizing part 14. The part 14 outputs information on a dynamic timing inspection applying part to a corresponding logical hierarchy recognizing part 15 to automatically recognize clock information.

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