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1. 发明专利

JPH05252188A 失效
公开(公告)号：JPH05252188A
公开(公告)日：1993-09-28
申请号：JP5005692
申请日：1992-03-06
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD , NEC CORP
发明人： ASHI MASAHIRO , TAKATORI MASAHIRO , NAKANO YUKIO , TAKASE MASAHIKO , UEDA HIROMI , NAKAJIMA TAKASHI , TAKEO HIROSHI , KAWAI MASAAKI , TANIGUCHI IKUO , KURANO TAKANORI , NISHIHARA MOTOO
IPC分类号： H04L7/00 , H04L12/28 , H04L12/48
摘要： PURPOSE:To distinguish an in-device generated empty cell from other cells by newly generating an empty cell at the time of transfer of timing and outputting specific information. CONSTITUTION:A write address control circuit 16 inputs a transmission line extraction timing signal 3 and controls operation for writing a cell in a cell buffer 12 according to a clock extracted from the reception signal of an ATM transmission line. Further, a phase supervisory and control circuit 17 is equipped with a means which monitors the phase of write timing and inserts an empty cell when there is no cell stored in the cell buffer 12 or when a cell buffer number becomes less than a predetermined numeral. Then an emptiness marker adding circuit 13 outputs information indicating a generated empty cell when the phase supervisory and control circuit 17 newly generates the empty cell. The phase supervisory and control circuit 17 and emptiness marker adding circuit 13 are provided with an empty cell generating means and a monitor means which outputs information for distinguishing the in-device empty cell from other cells.

2. 发明专利

JPH05327757A MONITOR CELL INSERTION CONTROL SYSTEM 失效
公开(公告)号：JPH05327757A
公开(公告)日：1993-12-10
申请号：JP13481792
申请日：1992-05-27
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , NEC CORP , HITACHI LTD
发明人： YAMASHITA HARUO , KAWAI MASAAKI , KOYANAGI TOSHINORI , KONDO RYUICHI , WAKIZAKA TAKAAKI , SUDO TOSHIYUKI , SATO HIROYUKI , UEDA HIROMI , AKUTSU KENJI , YASUDA TORU , MIYAMOTO AKIHIRO , ASHI MASAHIRO , SAITO KIYOSHI
IPC分类号： H04L12/24 , H04L12/26 , H04L12/48
摘要： PURPOSE:To insert a monitor cell at a designed position and to facilitate even the monitor of a duplex constitution in regard of a monitor cell insertion control system which monitors the inside of a cell processor. CONSTITUTION:A monitor cell inserting cell generating part 1 is provided together with a monitor cell inserting part 2, and a monitor cell extracting part 3. A monitor cell inserting cell is formed in a user cell train at the part 1. In a duplex constitution of 0 and 1 systems, the monitor cell inserting cells are formed in the same timing in both 0 and 1 systems. The part 2 detects the monitor cell inserting cell through a detecting part 6 and controls a selector 5. Then the part 2 selects and outputs the monitor cells held in a buffer memory 4 in order to insert and transfer the monitor cells. The part 3 extracts these monitor cells and collates them with each other to monitor the normal state of a transfer path.

3. 发明专利

JPH0998170A SYNCHRONIZING CONTROLLER FOR DOUPLEX DATA 失效
公开(公告)号：JPH0998170A
公开(公告)日：1997-04-08
申请号：JP25476695
申请日：1995-10-02
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： CHIBA YOSHINORI , KOBAYASHI KATSUMI , KUTSUZAWA TAKASHI , SATO YOSHIKO , ABIRU SETSUO , KAWAI MASAAKI , OKUMURA YASUYUKI
IPC分类号： H04L1/22 , H04L7/00 , H04L12/28 , H04Q3/00
摘要： PROBLEM TO BE SOLVED: To prevent transmission quality degradation caused by the omission of cells at a transmission system on the following stage by establishing synchronism in a short time for data dispatched through the transmission line of a different phase to the reception side. SOLUTION: This device is provided with '0' system and '1' system memories 11 and 12 for independently writing and reading cells while having capacitance for maximum phase difference between '0' system and '1' system data at least. Then, this device is provided with '0' system and '1' system cell memories 21 and 22 for storing haunching cells to be continuously read out at the time of haunching, when capacitance is just for one cell. Then, the coincidence of cells read from the memories 21 and 12 is discriminated by a 1st cell comparator circuit 31, the coincidence of cells read from the memories 11 and 22 is discriminated by a 2nd cell comparator circuit 32, further, the coincidence of cells read from the memories 11 and 12 is discriminated by a 3rd cell comparator circuit 33 respectively and outputs S0, S1 and M are outputted. Thus, haunching is simultaneously performed at the '0' system and '1' system and a read control means 4 discriminates which system is advanced corresponding to the outputs S0, S1 and M. Then, the cells are read from the memories 11 and 12 and just after the coincidence is detected, they are sent to the following stages by judging the establishment of synchronism.

4. 发明专利

JPH08139709A UNINTERRUPTIBLE SWITCHING SYSTEM 失效
公开(公告)号：JPH08139709A
公开(公告)日：1996-05-31
申请号：JP27401794
申请日：1994-11-08
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： HIROTA MASAKI , KAWAI MASAAKI , SHINOMIYA TOMOHIRO , TAJIMA KAZUYUKI , ABIRU SETSUO , MIYABE MASATAKE , OKUMURA YASUYUKI
IPC分类号： H04L1/22 , H04L12/28 , H04L12/70 , H04L12/56
摘要： PURPOSE: To attain a an uninterruptible switching operation by storing once the collected data and then retrieving the coincident data to carry out the switching operation. CONSTITUTION: A separator means 101 of a master device 100 separates a fixed quantity of data which are sent from each slave device 200 in time series via a transmission line 300 in response to the transmitter devices 200. A store means 102 stores the data separated by the means 101 for each device 200 in the order of earlier arrival. Thus the received data on the device 100 are stored in the order of earlier arrival and in response to the devices 200. Therefore, an interruptible switching operation can be carried out after the coincident data are detected and the reliability of a communication system can be improved.

5. 发明专利

JPH05227041A ONE-BIT ERROR CORRECTING CIRCUIT BASED UPON CRC OPERATION 失效
公开(公告)号：JPH05227041A
公开(公告)日：1993-09-03
申请号：JP5876892
申请日：1992-02-13
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： KAWAI MASAAKI , SEKIDO MASAMI , TAKIZAWA YUJI , NAITO HIDETOSHI , IKEDA TOSHIMI , TAJIMA KAZUYUKI , YAMASHITA HARUO , TATSUNO HIDEO
IPC分类号： H03M13/00 , H03M13/09 , H03M13/15 , H04L1/00
摘要： PURPOSE:To provide an one-bit error correcting circuit based on CRC operation which can be contracted at its size and reduced at its cost by providing the circuit with an one-bit error detecting means, a main signal reproducing means and a correcting means. CONSTITUTION:The one-bit error detecting means 41 decodes residual data obtained by circulating syndrome S to a 1st residual computing means 47 and detects one-bit error data. The main signal reproducing means 42 finds out exclusive OR 51 between residual data obtained from the output data of a prescribed register 19 in a cancel type syndrome forming part 11 through a 1st residual computing means 50 and data supplied from a prescribed register 18 and obtains main signal parallel data. The correcting means 43 finds out exclusive OR 54 between the parallel data obtained by the means 42 and the one-bit error data detected by the means 41 and finds out correction data H1' to H5'. The number of constitutional parts of each of these means 41 to 43 is remarkably reduced as compared with that of an error correction part in the one-bit error correcting circuit corresponding to the means 41 to 43.

6. 发明专利

JPH0530128A DEVICE MONITORING SYSTEM 失效
公开(公告)号：JPH0530128A
公开(公告)日：1993-02-05
申请号：JP16003791
申请日：1991-06-03
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKIZAWA YUJI , KAWAI MASAAKI , NAITO HIDETOSHI , WATABE HISAKO , TAJIMA KAZUYUKI , YAMASHITA HARUO
IPC分类号： H04L12/70 , H04Q11/04
摘要： PURPOSE:To provide a monitoring system which can insert and extract an intra-device monitoring OAM cell in the same interface part by providing loop back parts between multiplex parts and separation parts for interface parts. CONSTITUTION:When the intra-device monitoring OAM cell C inserted from the interface parts 101-10N and into which prescribed loop back information are written reaches the loop back parts 201-20N provided on a device using the cell for information transmission, the loop back parts 201-20N rewrite loop back information. Then, original loop back information is comparison-collated with rewritten loop back information in an OAM cell C' returned to the interface parts 101-10M, and it is judged whether the operation of the device normally functions or not. Thus, the monitoring system which can insert and extract the intra-device monitoring OAM cell in the same interface part of the device using the cell for information transmission can be realized and a processing can be simplified with such constitution.

7. 发明专利

JPS543407A CONTROL SYSTEM FOR LINE CONCENTRATION MULTIPLYING DEVICE FOR NONNSYNCHRONOUS TERMINAL 失效
公开(公告)号：JPS543407A
公开(公告)日：1979-01-11
申请号：JP6812777
申请日：1977-06-09
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： NAGATA ITSUO , KOMORI HIDEO , MOURI RIKUROU , KAWAI MASAAKI
IPC分类号： H04Q11/04
摘要： PURPOSE:To ensure a control of the line concentration multiplying device for the non-synchronous terminal with reduction of the communication time slot by using the s-bit contained in the envelope comprising the synchronous bits and others for the non-synchronous terminal as the control channel.

8. 发明专利

JPH10200514A TRANSMISSION QUALITY SUPERVISORY DEVICE 失效
公开(公告)号：JPH10200514A
公开(公告)日：1998-07-31
申请号：JP279397
申请日：1997-01-10
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAJIMA KAZUYUKI , SHINOMIYA TOMOHIRO , ABIRU SETSUO , HIROTA MASAKI , MIYABE MASATAKE , KAWAI MASAAKI , TAKIGAWA YOSHIHIRO
IPC分类号： H04L1/00 , H04B3/46
摘要： PROBLEM TO BE SOLVED: To supervise a transmission quality, even for transmission line that has a low transmission quality with high accuracy by discriminating whether or not a bit error on plural bits occurs in every small set, in addition to a BIP system that discriminates whether or not a bit error occurs in a signal bit in each small set. SOLUTION: A discriminating means 11 discriminates the existence of a bit error based on a BIP system about N sets, that are decided in the order or time sequence and consist of plural bits among bits which are separately included in a fetched frame. On the other hand, and error-detecting means 12 decodes a specific field and calculates a bit string that shows whether or not a bit error occurs to a bit unit. Error bit number detecting means 13-1 to 13-N divide calculated bit strings into N small sets, and discriminates whether or not the number of bits that have bit errors is plural. A supervisory result outputting means 14 multiplexes the result of the discrimination and the logical OR of a discrimination result of the means 13-1 to 13-N and outputs it.

9. 发明专利

JPH0983500A BURST SYNCHRONOUS CIRCUIT 失效
公开(公告)号：JPH0983500A
公开(公告)日：1997-03-28
申请号：JP23024395
申请日：1995-09-07
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： HIROTA MASAKI , KAWAI MASAAKI , SHINOMIYA TOMOHIRO , TAJIMA KAZUYUKI , ABIRU SETSUO , MIYABE MASATAKE , HARADA KENJI , TAKIGAWA KOUHIROU
IPC分类号： H04L7/00 , H04L7/02
摘要： PROBLEM TO BE SOLVED: To provide a burst synchronous circuit in a receiver between communi cation equipments making burst transmission so as to receive burst data proper ly. SOLUTION: The burst synchronization circuit is used to match a bit phase of burst data BD received by a receiver between communication equipments for burst transmission based on a clock signal CLK. After a means 21 delays the data BD by picture phase amount and plural data are outputted by triggering with the CLK and a means 22 detects one change point with different logic adjacent to plural output data from the means 21. Thus, one side edge is detected and a means 23 is used to obtain an optimum phase entering a safe region at which the CLK points out properly data by adding a prescribed phase to a phase of one side edge. Then data of an optimum phase obtained by the means 23 are selected and outputted among plural output data of the means 21.

10. 发明专利

JPH0974418A DATA CELL MULTIPLEXING CIRCUIT 失效
公开(公告)号：JPH0974418A
公开(公告)日：1997-03-18
申请号：JP22919995
申请日：1995-09-06
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAJIMA KAZUYUKI , KAWAI MASAAKI , SHINOMIYA TOMOHIRO , ABIRU SETSUO , HIROTA MASAKI , MIYABE MASATAKE , KAJIWARA TAKAFUMI
IPC分类号： H04Q3/00 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To simply and inexpensively realize the data cell multiplexing circuit. SOLUTION: The data cell multiplexing circuit is configured by including plural buffer means 11 provided corresponding to plural inputs respectively and storing sequentially data cells to be transferred for output, a multiplexing means 12 multiplexing and transferring the data cells, other components such as a buffer control means 21, a transmission control means 22, a register means 23 and an output discrimination means 24. The buffer control means 21 controls write/read to/from the buffer means 11 and outputs a cell presence display signal S1. The transmission control means 22 controls the transmission/non- transmission of the signal S1. The register means 23 stores each cell presence display signal S1. The output discrimination means 24 monitors the means 23 to discriminate whether or not the signal S1 is outputted from an input at a higher priority than its own priority and commands the cell read to the means 21 when not outputted.

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