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1. 发明专利

JP2004063527A Semiconductor memory device and its manufacturing method 审中-公开
公开(公告)号：JP2004063527A
公开(公告)日：2004-02-26
申请号：JP2002216112
申请日：2002-07-25
申请人： Elpida Memory Inc , Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： OYU SHIZUNORI , OGISHIMA JUNJI , UCHIYAMA HIROYUKI , KAWAKITA KEIZO , SUZUKI MASATO
IPC分类号： H01L21/76 , H01L21/265 , H01L21/336 , H01L21/762 , H01L21/8234 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/76237 , H01L21/26586 , H01L21/823481 , H01L27/10873
摘要： PROBLEM TO BE SOLVED: To prevent the refreshing characteristics deteriorated by the influence of adjacent word lines of adjacent cells and to enable to reduce defects a after packaging and reflowing. SOLUTION: An active region 1 has a diffused layer in a region sandwiched between word lines 4, 2, 3 and 5. The diffused layer 6 sandwiched between the word lines 2 and 3 is connected to a bit line via a contact, and a diffused layer 7 sandwiched between the word lines 2 and 4 and a diffused layer 8 sandwiched between the word lines 3 and 5 are connected to respective capacities through a contact. A cell structure has two cell transistors in which the word line 2 is used as a gate electrode, and the diffused layers 6, 7 are used as source/drain. In the structure, the word line 3 is used as a gate electrode, and the diffused layers 6, 8 are used as source/drain. N-type diffused layers 7, 8 formed of the word lines 2, 3 adjacent to the word lines 4, 5 have a high n-type carrier concentration at the word lines 4, 5 sides from the word lines 2, 3 sides, or a p-type substrate concentration is set to a low concentration at the word lines 4, 5 sides. COPYRIGHT: (C)2004,JPO

2. 发明专利

JP2004342733A Method of manufacturing semiconductor device and semiconductor device manufactured therethrough 有权
公开(公告)号：JP2004342733A
公开(公告)日：2004-12-02
申请号：JP2003135668
申请日：2003-05-14
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： SHINODA KAZUNORI , UCHIYAMA HIROYUKI , OTA HIROSHI
IPC分类号： H01L21/331 , H01L21/308 , H01L21/338 , H01L27/15 , H01L29/737 , H01L29/778 , H01L29/812 , H01S5/227
摘要： PROBLEM TO BE SOLVED: To realize a wet etching method which produces no oxide on the surface of a semiconductor and to provide a semiconductor device which is much improved in performance and reliability.
SOLUTION: In the method of manufacturing the semiconductor device having a process of etching a compound semiconductor with an etching solution, the etching solution includes chemical materials containing group 6B atoms as constitution elements, the atomic numbers of all group 6B atoms forming the chemical materials are 16 or above (e.g. all group 6B atoms forming the chemical materials are sulfur atoms), and the compound semiconductor is etched with the above etching solution.
COPYRIGHT: (C)2005,JPO&NCIPI

3. 发明专利

JP2012204560A Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012204560A
公开(公告)日：2012-10-22
申请号：JP2011067054
申请日：2011-03-25
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： UCHIYAMA HIROYUKI
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10855 , H01L27/10852 , H01L28/91
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which a bit line is linear and a cell transistor in a longitudinal direction is parallel with a bit line direction, and further, the bit line is wired on a location overlapping the cell transistor when viewed from above.SOLUTION: A semiconductor device comprises: a bit line BL provided on a top face of first and second contact plugs 6a, 6b via a first insulation layer 10a and extending in a direction linking a first impurity diffusion layer 4a and a second impurity diffusion layer 4b; a bit line contact plug provided to penetrate the first insulation layer 10a and electrically connecting the bit line BL with the first contact plug 6a; a first cell capacitor having a first lower electrode 7a at a location lateral to one lateral face side of the bit line BL; a first insulation film 8a insulating the bit line BL and the first lower electrode 7a; and a first contact conductor 9a electrically connecting a lower end of the first lower electrode 7a with a lateral face of the second contact plug 6b.
摘要翻译：要解决的问题：提供一种半导体器件，其中位线是线性的，并且单元晶体管在纵向方向上与位线方向平行，此外，位线被布线在与单元格重叠的位置晶体管。解决方案：半导体器件包括：位线BL，其经由第一绝缘层10a设置在第一和第二接触插头6a，6b的顶面上，并且沿着连接第一杂质扩散层4a和第二杂质的方向延伸扩散层4b; 设置为穿透第一绝缘层10a并将位线BL与第一接触插头6a电连接的位线接触插塞; 第一单电池电容器，具有位于位线BL的一个侧面侧的位置的第一下电极7a; 使位线BL和第一下电极7a绝缘的第一绝缘膜8a; 以及将第一下电极7a的下端与第二接触插塞6b的侧面电连接的第一接触导体9a。版权所有（C）2013，JPO＆INPIT

4. 发明专利

JP2009123882A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009123882A
公开(公告)日：2009-06-04
申请号：JP2007295770
申请日：2007-11-14
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： UCHIYAMA HIROYUKI
IPC分类号： H01L29/786 , H01L21/28 , H01L21/768 , H01L21/8234 , H01L23/522 , H01L27/00 , H01L27/088 , H01L29/41 , H01L29/423 , H01L29/49
CPC分类号： H01L29/78642 , H01L27/12
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that includes field-effect transistors having a structure allowing high-density mounting.
SOLUTION: The semiconductor device has: a substrate; a first insulating layer provided on the substrate; a conductive layer embedded into the first insulating layer; a pillar-shaped semiconductor part having a lower diffusion layer that is electrically connected with the conductive layer and is disposed just above the conductive layer, a semiconductor layer on the lower diffusion layer, and an upper diffusion layer on the semiconductor layer; a gate insulating film provided at the peripheral lateral side of the semiconductor layer; a gate electrode provided on the gate insulating film; and a second insulating layer provided to embed the gate electrode and the pillar-shaped semiconductor part.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种包括具有允许高密度安装的结构的场效应晶体管的半导体器件。解决方案：半导体器件具有：衬底; 设置在所述基板上的第一绝缘层; 嵌入到所述第一绝缘层中的导电层; 柱状半导体部件，具有与导电层电连接并设置在导电层正上方的下扩散层，下扩散层上的半导体层和半导体层上的上扩散层; 设置在半导体层的外周侧的栅极绝缘膜; 设置在所述栅极绝缘膜上的栅电极; 以及设置成嵌入栅电极和柱状半导体部件的第二绝缘层。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2007189009A Semiconductor device and its fabrication process 有权
标题翻译：半导体器件及其制造工艺
公开(公告)号：JP2007189009A
公开(公告)日：2007-07-26
申请号：JP2006004827
申请日：2006-01-12
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： UCHIYAMA HIROYUKI
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L28/90 , H01L27/10897
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which complication of fabrication process is suppressed and the capacity of a capacitor for storing data is increased.
SOLUTION: A plurality of wiring layers are provided in the peripheral circuit portion and the memory cell has a capacitor where a plate electrode, a capacitance insulating film formed on the sidewall of an opening in the plate electrode, and a storage electrode buried in the opening where the capacitance insulating film is formed on the sidewall are provided in correspondence with the plurality of wiring layers and the storage electrodes are connected with each other.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体器件，其中制造工艺的复杂性被抑制，并且用于存储数据的电容器的容量增加。解决方案：在外围电路部分设置多个布线层，并且存储单元具有电容器，其中板电极，形成在平板电极的开口的侧壁上的电容绝缘膜和埋置的存储电极在与多个布线层对应地设置有在侧壁上形成电容绝缘膜的开口中，并且存储电极彼此连接。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2011187472A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2011187472A
公开(公告)日：2011-09-22
申请号：JP2010047853
申请日：2010-03-04
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： UCHIYAMA HIROYUKI
IPC分类号： H01L21/82 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device used for an anti-fuse element, which achieves stable operations as the anti-fuse element by reducing variation in a resistance value in a conduction state. SOLUTION: The semiconductor device has an active field 11 formed on the main surface of a semiconductor substrate 1, and a gate electrode 12 provided on the active field 11 via a gate insulating film 5 formed on the front surface of the active field 11. The gate electrode 12 is disposed so as to be surrounded by the active field 11 when viewed from a plan view of the main surface of the semiconductor substrate 1, and so that the periphery of the gate electrode 12 overlaps on the active field 11 disposed on the surrounding of the gate electrode 12 to form an overlapped region 13. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于抗熔丝元件的半导体器件，其通过减小导通状态下的电阻值的变化而实现作为反熔丝元件的稳定操作。解决方案：半导体器件具有形成在半导体衬底1的主表面上的有源场11和通过形成在有源场的前表面上的栅极绝缘膜5设置在有源场11上的栅电极12 当从半导体衬底1的主表面的平面图观察时，栅电极12被设置成被有源场11包围，并且使得栅电极12的外围与有源场11重叠设置在栅电极12的周围以形成重叠区域13.版权所有（C）2011，JPO＆INPIT

7. 发明专利

JP2011091254A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011091254A
公开(公告)日：2011-05-06
申请号：JP2009244455
申请日：2009-10-23
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： UCHIYAMA HIROYUKI
IPC分类号： H01L27/108 , H01L21/8242
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device coping with further refining and higher integration while increasing the capacitance value per unit volume, and to provide a method of manufacturing the same.
SOLUTION: A capacitor structure 10 has a structure that constitutes a laminate 17 formed by alternately laminating a plurality of first conductive films 12a-12c constituting a storage electrode 12 with capacitance insulating films 11a-11e interposed, and a plurality of second conductive films 13a-13c constituting an counter electrode 13. The plurality of first conductive films 12a-12c are connected by a first connection conductor 21a with the plurality of first conductive films 12a-12c exposed from one end surface 17a of the laminate 17, and the plurality of second conductive films 13a-13c are connected by a second connection conductor 21b with the plurality of second conductive films 13a-13c exposed from the other end surface of the laminate 17.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种半导体器件，能够在增加每单位体积的电容值的同时进一步精炼和更高的集成，并提供其制造方法。解决方案：电容器结构10具有构成层叠体17的结构，该层压体17通过交替层叠构成存储电极12的多个第一导电膜12a-12c与插入的电容绝缘膜11a-11e而形成，并且多个第二导电多个第一导电膜12a-12c通过第一连接导体21a连接，多个第一导电膜12a-12c从层压体17的一个端面17a露出，并且多个第二导电膜13a-13c通过第二连接导体21b连接，多个第二导电膜13a-13c从层压体17的另一个端面露出。（C）2011，JPO＆INPIT

8. 发明专利

JP2010219326A Semiconductor memory device and method of manufacturing the same 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2010219326A
公开(公告)日：2010-09-30
申请号：JP2009064798
申请日：2009-03-17
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： UCHIYAMA HIROYUKI
IPC分类号： H01L21/8242 , H01L21/768 , H01L27/105 , H01L27/108 , H01L29/41 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L27/10876 , H01L29/66666 , H01L29/7827
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device having a three-dimensional transistor which is highly integrated and is not required to embed a bit line.
SOLUTION: A semiconductor memory device includes an active region having first and second diffusion layers located on both sides through a gate trench and a third diffusion layer formed on the bottom of the gate trench, first and second memory elements which are connected with the first and second diffusion layers, respectively, a bit line connected with the third diffusion layer, a first gate electrode covering the first side of the gate trench through the gate insulating film and forming a channel between the first diffusion layer and the third diffusion layer, and a second gate electrode covering the second side of the gate trench through the gate insulating film and forming a channel between the second diffusion layer and the third diffusion layer. According to the present invention, different transistors are individually formed on both sides of the gate trench, so the degree of integration that is the double of those of the conventional devices can be obtained.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有高度集成并且不需要嵌入位线的三维晶体管的半导体存储器件。解决方案：半导体存储器件包括有源区，其具有通过栅极沟槽位于两侧的第一和第二扩散层，以及形成在栅极沟槽的底部上的第三扩散层，第一和第二存储元件与所述第一和第二扩散层分别与所述第三扩散层连接的位线，通过所述栅极绝缘膜覆盖所述栅极沟槽的第一侧的第一栅电极，并且在所述第一扩散层和所述第三扩散层之间形成沟道以及第二栅电极，其通过栅极绝缘膜覆盖栅极沟槽的第二侧，并在第二扩散层和第三扩散层之间形成沟道。根据本发明，在栅极沟槽的两侧分别形成不同的晶体管，因此可以获得与常规器件的整合度的两倍的积分度。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2010016168A Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010016168A
公开(公告)日：2010-01-21
申请号：JP2008174605
申请日：2008-07-03
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： UCHIYAMA HIROYUKI
IPC分类号： H01L21/8242 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/417 , H01L29/423 , H01L29/49
CPC分类号： H01L27/24 , H01L21/823418 , H01L21/823475 , H01L27/0629 , H01L29/66621
摘要： PROBLEM TO BE SOLVED: To provide a finer semiconductor device. SOLUTION: A semiconductor device includes a plurality of MOS transistors including a source electrode and a drain electrode formed in a region from the surface of a substrate to a prescribed depth and a gate electrode formed in a position deeper in the substrate than the two electrodes. The semiconductor device also includes wiring connected to the source electrode or drain electrode of the plurality of MOS transistors, and formed in the same layer as the source electrode and the drain electrode in a substrate, or in a position deeper than the surface of the substrate. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供更精细的半导体器件。解决方案：半导体器件包括多个MOS晶体管，其包括源极电极和漏电极，所述源极电极和漏电极形成在从衬底的表面到规定深度的区域中，栅电极形成在衬底中比位于衬底中更深的位置两个电极。半导体器件还包括连接到多个MOS晶体管的源电极或漏电极的布线，并且与衬底中的源电极和漏极形成在相同的层中，或者形成在比衬底的表面更深的位置。版权所有（C）2010，JPO＆INPIT

10. 发明专利

JP2007036267A Method for forming sog film 审中-公开
标题翻译：形成SOG膜的方法
公开(公告)号：JP2007036267A
公开(公告)日：2007-02-08
申请号：JP2006239148
申请日：2006-09-04
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： SAITO MASAYOSHI , HOTTA KATSUHIKO , HIRASAWA MASANARI , KOJIMA MASAYUKI , UCHIYAMA HIROYUKI , MARUYAMA HIROYUKI , FUKUDA TAKUYA
IPC分类号： H01L21/312 , H01L21/316 , H01L21/76 , H01L21/768 , H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide an insulating film forming technology for miniaturizing an MISFET.
SOLUTION: An SOG film 16 formed by carrying out heat treatment to an HSQ-SOG film at a temperature of about 800°C is used as a flattened insulating film formed on the gate electrode 9 of an MISFET(Qs, Qn, Qp). Also, an HSQ-SOG film 57 whose high temperature heat treatment is not carried out is used as an inter-film insulating film between wiring (54, 55, 56, 62 and 63) of an upper layer.
COPYRIGHT: (C)2007,JPO&INPIT

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