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1. 发明公开

EP4101089A1 DYNAMIC TRANSMITTER PROCESSING MODIFICATION 审中-实审
公开(公告)号：EP4101089A1
公开(公告)日：2022-12-14
申请号：EP21750838.1
申请日：2021-02-02
申请人： Texas Instruments Incorporated
发明人： FAN, Yanli , RANE, Amit
IPC分类号： H04B17/17 , H04L25/40 , H03F3/72

2. 发明公开

EP3777061A1 SENDING INFORMATION SIGNALS ON A DIFFERENTIAL SIGNAL PAIR 审中-公开
公开(公告)号：EP3777061A1
公开(公告)日：2021-02-17
申请号：EP19785359.1
申请日：2019-04-09
申请人： ClearOne, Inc.
发明人： THURMOND, Ed , EGAN, Charles
IPC分类号： H04L25/02 , H04L25/40 , H04L25/03

3. 发明公开

EP3020173A4 SYSTEM AND METHOD FOR ITERATIVE COMPENSATION FOR LINEAR AND NONLINEAR INTERFERENCE IN SYSTEM EMPLOYING FTN SYMBOL TRANSMISSION RATES 有权
标题翻译：系统和方法的线性和非线性问题迭代补偿系统中的带符号FTN传输速率
公开(公告)号：EP3020173A4
公开(公告)日：2017-03-22
申请号：EP14822126
申请日：2014-07-08
申请人： HUGHES NETWORK SYSTEMS LLC
发明人： BEIDAS BASSEL , SESHADRI ROHIT LYER , EROZ MUSTAFA , LEE LIN-NAN
IPC分类号： H04L25/40 , H04L1/00 , H04L25/03 , H04L25/497
CPC分类号： H04L25/03006 , H04L1/0048 , H04L1/005 , H04L1/0054 , H04L25/0314 , H04L25/03165 , H04L25/03834 , H04L25/497
摘要： An approach for increasing transmission throughput of a non-linear wireless channel, and efficient decoding of the transmitted signal via a simplified receiver, is provided. A signal reflects a source signal, and includes linear inter-symbol interference based on a faster-than-Nyquist signaling rate and a tight frequency roll-off, and non-linear interference based on high-power amplification for transmission over the wireless channel. The signal is received over a non-linear wireless channel, and is processed via a plurality of decoding iterations. A set of soft information of a current decoding iteration is generated based on a current estimate of the source signal and a final set of soft information from a previous decoding iteration. The current estimate of the source signal is based on an estimate of the linear ISI and the non-linear interference, which is based on the final set of soft information from the previous decoding iteration.

4. 发明授权

EP2091193B1 A SIGNAL PROCESSING SYSTEM, CHIP, EXTERNAL CARD, FILTER DEVICE AND SIGNAL PROCESSING METHOD 有权
标题翻译：设备，芯片，外部基板和过滤嘴信号处理和相关的方法
公开(公告)号：EP2091193B1
公开(公告)日：2016-05-18
申请号：EP07846023.5
申请日：2007-12-05
申请人： Huawei Technologies Co., Ltd.
发明人： FANG, Liming
IPC分类号： H04L25/40 , H04B3/32
CPC分类号： H04B3/30 , H04B3/32

5. 发明公开

EP2735102A2 SELECTIVE-SAMPLING RECEIVER 审中-公开
标题翻译：选择性扫描接收机
公开(公告)号：EP2735102A2
公开(公告)日：2014-05-28
申请号：EP12815594.2
申请日：2012-07-20
申请人： Weber, Daniel
发明人： Weber, Daniel
IPC分类号： H04B1/10 , H04L25/40 , H04L27/00
CPC分类号： G01S7/023 , G01S7/2813 , G01S7/36
摘要： A receiver that selectively samples a received signal in order to suppress an interference component of the signal while recovering a desired component. The selective sampling may be accomplished by low cost, low complex analog or digital circuitry. The receiver includes a first input that receives a first signal, including a desired signal component and an interference signal component and a second input that receives a second signal including the interference component only. The first and second signals are then provided to the sampling circuitry. First, the phase of the interference component of the both the first and second signals is aligned. Next, the points in a wave cycle that the second signal is at a power minimum are detected. Finally, first signal is sampled close to the point when the second signal is at the power minimum to recover the desired signal component and suppress the interference component.

6. 发明公开

EP2506433A1 TRANSMITTING DEVICE, RECEIVING DEVICE AND TRANSMITTING/RECEIVING SYSTEM 审中-公开
标题翻译： SENDEVORRICHTUNG，EMPFANGSVORRICHTUNG UND SENDE-EMPFANGSSYSTEM
公开(公告)号：EP2506433A1
公开(公告)日：2012-10-03
申请号：EP11814362.7
申请日：2011-06-02
申请人： Thine Electronics, Inc.
发明人： AKITA Hironobu
IPC分类号： H03K5/156 , H03K5/00 , H04L7/04 , H04L25/40
CPC分类号： H04B1/0475 , H04B15/04 , H04B15/06 , H04L7/0008 , H04L7/0337
摘要： A transmitting device 10A has a transmission data generating part 11 and an output buffer part 12A. The transmission data generating part 11 transmits a data 1 and a clock 1, which are to be transmitted to a receiving device, and outputs them to the output buffer part 12A. The output buffer part 12A includes a data transmitting part 13 and a clock transmitting part 14A. The clock transmitting part 14A generates and transmits a clock intermittently phase-shifted. The data transmitting part 13 transmits the data in sync with the clock transmitted from the clock transmitting part 14A.
摘要翻译：发送装置10A具有发送数据生成部11和输出缓冲部12A。发送数据生成部11发送要发送到接收装置的数据1和时钟1，并将其输出到输出缓冲器部分12A。输出缓冲器部分12A包括数据发送部分13和时钟发送部分14A。时钟发送部14A生成并发送间歇地相移的时钟。数据发送部13与从时钟发送部14A发送的时钟同步发送数据。

7. 发明公开

EP2136218A1 DATA RECEIVING CIRCUIT, TESTER USING SAME, AND TIMING ADJUSTING CIRCUIT FOR STROBE SIGNAL AND METHOD 审中-公开
标题翻译： DATENEMPFANGSSCHALTUNG，TESTER DAMIT UND TIMING-EINSTELLSCHALTUNGFÜREIN STROBE-SIGNAL UND VERFAHREN
公开(公告)号：EP2136218A1
公开(公告)日：2009-12-23
申请号：EP08720518.3
申请日：2008-03-18
申请人： Advantest Corporation
发明人： WATANABE, Daisuke , OKAYASU, Toshiyuki
IPC分类号： G01R31/319 , G01R35/00 , H04L25/40
CPC分类号： G01R31/3191 , G01R31/31937
摘要： A variable delay circuit 42 provides an adjustable delay to a strobe signal S5. An input latch circuit 14 latches each bit data included in internal serial data S2 by a strobe signal S6 delayed by the variable delay circuit 42. A delay set unit 40 adjusts a delay amount τ1 provided to the strobe signal S5 by the variable delay circuit 42. While a calibration operation is being executed in which a known calibration pattern is inputted as serial data, the delay set unit 40 statistically acquires output latch data S3 of the input latch circuit 14, and adjusts the delay amount τ1 such that probabilities of occurrence of 1 and 0 becomes a predetermined ratio.
摘要翻译：可变延迟电路42为选通信号S5提供可调延迟。输入锁存电路14将包含在内部串行数据S2中的每个比特数据锁存在由可变延迟电路42延迟的选通信号S6上。延迟设定单元40通过可变延迟电路42调整提供给选通信号S5的延迟量Ä1 当正在执行其中输入已知校准图案作为串行数据的校准操作时，延迟设定单元40统计地获取输入锁存电路14的输出锁存数据S3，并调整延迟量Ä1，使得发生概率 1和0成为预定比例。

8. 发明公开

EP2034683A1 Verfahren zum Auswerten von Empfangssignalen bei serieller Datenübertragung 审中-公开
标题翻译：维特根王妃on on on on on eller eller eller eller eller eller eller eller eller eller eller eller eller eller
公开(公告)号：EP2034683A1
公开(公告)日：2009-03-11
申请号：EP07115613.7
申请日：2007-09-04
申请人： Siemens Aktiengesellschaft Österreich
发明人： Sterz, Walter
IPC分类号： H04L25/06 , H04L25/40 , H04L7/033
CPC分类号： H04L7/033 , H04L25/068 , H04L25/4906
摘要： Die Erfindung betrifft Verfahren zum Auswerten von Empfangssignalen bei serieller Datenübertragung, wobei ein Empfangssignal aus einer Anzahl von Abschnitten, insbesondere Worten, besteht. Dabei weisen die Abschnitte, insbesondere die Worte, zwischen einem Start- und Stopppunkt eine definierte Länge und eine definierte Zahl von Informationseinheiten, insbesondere Bits, auf. Dabei werden die Informationseinheiten jedes Abschnittes des Empfangssignals über die definierte Länge des Abschnittes n-fach abgetastet (2,3). Dann werden während einer Abtastung ermittelte Abtastwerte für den jeweiligen Abschnitt in zeitlicher Reihenfolge abgespeichert (4), wobei jede ununterbrochene Folge von gleichwertigen Abtastwerten einen High- bzw. Lowbereich definiert (5) . Daraufhin wird dann anhand der durch die Anzahl an aufeinanderfolgenden, gleichwertigen Abtastwerte bestimmten Länge des High- bzw. Lowbereiches die darin enthaltene Anzahl von entsprechenden Informationseinheiten bestimmt (6,7).
摘要翻译：该方法包括在部分（3）的限定长度上扫描接收信号的部分信息单元n次。在扫描期间按照时间顺序存储相应部分的确定的扫描值（4）。等效扫描值的每个连续序列定义了高或低的面积。基于通过连续等效扫描值的数量确定的高低区域的长度来确定对应的信息单元的数量（6）。工业标准 - 使用称为电子工业协会-42接口的异步串行接口。

9. 发明公开

EP0774849A3 Verfahren zum Übertragen von binären, asynchronen Daten über einen synchronen Kanal 失效
标题翻译：用于在同步信道上发送二进制，异步数据的方法
公开(公告)号：EP0774849A3
公开(公告)日：2000-09-06
申请号：EP96810751.6
申请日：1996-11-07
申请人： ABB Power Automation AG
发明人： Scherwey, Roland
IPC分类号： H04L25/40
CPC分类号： H04L25/40
摘要： Es wird ein Verfahren zum Übertragen von binären, asynchronen Daten, mit einer Datenwortbreite von N Bit, von einem Sender über einen synchronen Kanal zu einem Empfänger angegeben. Dadurch, dass die Datenwörter aus den asynchronen Daten extrahiert und codiert auf zu übertragende Rahmenwörter eines Rahmens aufgeteilt werden, erreicht man eine maximale Ausnutzung der Übertragungskapazität des synchronen Kanals.

10. 发明公开

EP0744099A4 INTERFERENCE DEPENDENT ADAPTIVE PHASE CLOCK CONTROLLER 失效
标题翻译：电路是否干扰变化的自适应时钟控制
公开(公告)号：EP0744099A4
公开(公告)日：1999-09-01
申请号：EP95939613
申请日：1995-10-27
申请人： MOTOROLA INC
发明人： CONNELL LAWRENCE EDWIN , KANG DAVID DUKHO , HOLLENBECK NEAL WAYNE , ROECKNER WILLIAM J
IPC分类号： G06J1/00 , H03M1/10 , H04L7/02 , H04L7/033 , H04B1/10 , H04L1/00 , H04L7/00 , H04L25/08 , H04L25/36 , H04L25/40
CPC分类号： H04L7/0054 , G06J1/00 , H03M1/1009 , H04L7/033 , H04L7/0334
摘要： An interference dependent adaptive phase clock controller method and system includes synthesis of a signal processing clock signal (307). An interference signal (311) dependent on a phase of the signal processing clock signal is measured, and a phase correction signal (317) is provided dependent thereon. A magnitude of the interference signal is reduced by adjusting the phase of the signal processing clock signal (307) dependent on the phase correction signal (317).

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