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3. 发明公开

EP4334801A1 INDEPENDENT CLOCKING FOR CONFIGURATION AND STATUS REGISTERS 审中-实审
公开(公告)号：EP4334801A1
公开(公告)日：2024-03-13
申请号：EP21749383.2
申请日：2021-06-22
申请人： Google LLC
发明人： PUTTI, Nagaraj Ashok
IPC分类号： G06F1/3237 , G06F1/04

4. 发明公开

EP4012534A1 MASKING A POWER STATE OF A CORE OF A PROCESSOR 审中-实审
公开(公告)号：EP4012534A1
公开(公告)日：2022-06-15
申请号：EP22154876.1
申请日：2016-06-14
申请人： Intel Corporation
发明人： Gendler, Alexander , Novakovsky, Larisa , Sistla, Krishnakanth V. , Garg, Vivek , Mulla, Dean , Choubal, Ashish V. , Hallnor, Erik G. , Weier, Kimberly C.
IPC分类号： G06F1/32 , G06F13/14 , G06F9/38 , G06F15/78 , G06F1/3203 , G06F1/04 , G06F15/163 , G06F1/3237 , G06F1/324 , G06F1/329 , G06F1/3234 , G06F1/3293 , G06F1/3287 , G06F12/0831
摘要： In one embodiment, a processor comprises a core to execute instructions and a core perimeter logic coupled to the core. The core perimeter logic includes a fabric interface logic having a first storage to store state information of the core when the core is in a low power state. The core perimeter logic is to enable an inter-die interconnect coupled between the core and an uncore to be maintained in an active state during entry of the core into a low power state. The fabric interface logic includes a snoop logic to receive a snoop request from a requester when the core is in the low power state and send a snoop response to the requester while the core is to remain in the low power state.

5. 发明公开

EP3771963A1 METHOD AND APPARATUS FOR BALANCING LOADS, AND COMPUTER-READABLE STORAGE MEDIUM 无效转让
公开(公告)号：EP3771963A1
公开(公告)日：2021-02-03
申请号：EP20165846.5
申请日：2020-03-26
申请人： BEIJING BAIDU NETCOM SCIENCE AND TECHNOLOGY CO. LTD.
发明人： Gu, Canghai , Wu, Peng
IPC分类号： G06F1/3206 , G06F1/3234 , G06F1/3287 , G06F1/3237
摘要： Embodiments of the present disclosure relate to a method and apparatus for balancing loads, and a computer-readable storage medium. The method includes: for each data processing unit in a set of data processing units in a data processing system, acquiring (310) current input data for the data processing unit in a current clock cycle and next input data for the data processing unit in a next clock cycle; and determining (320) a first metric value indicating changes in input data of said data processing unit in the next clock cycle based on a comparison between the current input data and the next input data. The method further includes controlling (330) an operating state of the set of data processing units in the next clock cycle based on the first metric value determined for the set of data processing units.

6. 发明公开

EP4436045A1 SEMICONDUCTOR DEVICE PERFORMING CLOCK GATING AND OPERATING METHOD THEREOF 审中-公开
公开(公告)号：EP4436045A1
公开(公告)日：2024-09-25
申请号：EP24164929.2
申请日：2024-03-20
申请人： Samsung Electronics Co., Ltd.
发明人： LEE, Jaeyoung , KIM, Byungsu , KIM, Youngsan , LEE, Jaegon , KIM, Jaehoon , LEE, Byeongho , LEE, Jongjin , JEONG, Wookyeong
IPC分类号： H03K19/00 , G06F1/10 , G06F1/3237
CPC分类号： H03K19/0016 , G06F1/10 , G06F1/3237
摘要： A semiconductor device (1) includes an intellectual property (IP) block (140) configured to operate based on a first clock signal (CLK_OUT) and a power voltage (VDDin), a clock gating circuit (130) configured to operate based on the power voltage, and generate the first clock signal (CLK_OUT) by selectively performing clock gating on a second clock signal (CLK_IN) based on an enable signal (En), and a critical path monitor (CPM, 120) configured to generate a digital code (CPM code) having a value, which varies according to a voltage drop of the power voltage (VDDin), and activate the enable signal (En) based on a comparison of the value of the digital code with a reference value.

8. 发明公开

EP4354250A1 CLOCK DISTRIBUTION NETWORK 审中-公开
公开(公告)号：EP4354250A1
公开(公告)日：2024-04-17
申请号：EP22201654.5
申请日：2022-10-14
申请人： EM Microelectronic-Marin SA
发明人： Ovidiu, SIMA
IPC分类号： G06F1/04 , G06F1/10 , G06F1/3237
CPC分类号： G06F1/10 , G06F1/04 , G06F1/3237
摘要： The present disclosure relates to a clock distribution network (10), comprising:
- a clock generator (14) configured to generate at least a processor clock signal and at least a first peripheral clock signal, the clock generator (14) further comprises at least a processor clock output (31), a first peripheral clock output (32) and a first clock request input (42),
- a processing unit (16) connected to the processor clock output (31) and configured to operate on a rising edge of the processor clock signal receivable via the processor clock output (31),
- at least a first peripheral unit (22) connected to the first peripheral clock output (32) and connected to the first clock request input (42) of the clock generator (14), wherein the at least first peripheral unit (22) is configured to operate on a falling edge of the first peripheral clock signal received via the first peripheral clock output (32),
- wherein the at least first peripheral unit (22) via the first clock request input (42) is operable to trigger the clock generator (14) to transmit the first peripheral clock signal via the first peripheral clock output (32).

9. 发明公开

EP4260174A1 DATA-TYPE-AWARE CLOCK-GATING 审中-实审
公开(公告)号：EP4260174A1
公开(公告)日：2023-10-18
申请号：EP21840398.8
申请日：2021-12-08
申请人： Amazon Technologies, Inc.
发明人： BOWMAN, Joshua Wayne , VOLPE, Thomas A. , AMIRINENI, Sundeep , DESAI, Nishith , DIAMANT, Ron
IPC分类号： G06F7/483 , G06F1/3237

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