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1. 发明授权

EP1889488B1 AUDIO-VIDEO PROCESSING SYSTEM 有权
标题翻译： AUDIO-视频处理系统
公开(公告)号：EP1889488B1
公开(公告)日：2012-10-31
申请号：EP06765672.8
申请日：2006-05-08
申请人： Trident Microsystems (Far East) Ltd.
发明人： VANDERHEIJDEN, Gerardus, W., T. , KATS, Romke , SNIJDERS, Richard, A., M., J.
IPC分类号： H04N7/56 , H04N5/60 , H04N5/067
CPC分类号： H04N21/44 , H04N5/0736 , H04N5/602 , H04N21/2368 , H04N21/4307 , H04N21/4341 , H04N21/439

2. 发明公开

EP2033434A1 METHOD AND APPARATUS FOR SYNCHRONIZING A GRAPHICS SIGNAL ACCORDING TO A REFERENCE SIGNAL 审中-公开
标题翻译：方法和设备，用于同步图形信号，以便根据参考信号
公开(公告)号：EP2033434A1
公开(公告)日：2009-03-11
申请号：EP07719705.1
申请日：2007-05-04
申请人： Miranda Technologies Inc.
发明人： NOORY, Robert , MARCOTTE, Sylvain
IPC分类号： H04N5/04
CPC分类号： H04N5/126 , G09G5/12 , G09G5/18 , H04N5/0736 , H04N5/44504 , H04N21/42653 , H04N21/4305 , H04N21/4307 , H04N21/8146
摘要： A method for synchronizing a graphics signal provided by a graphics generating unit according to a video reference signal, the method comprising receiving the graphics signal, receiving the video reference signal, comparing the graphics signal with the video reference signal to provide an error signal indicative of a synchronization between the video reference signal and the reference signal and using the error signal to perform a compensation at the graphics generating unit to provide a synchronized graphics signal.

3. 发明公开

EP1672910A1 Frame synchronizer, optical disk device, information recording/reproducing apparatus, and signal synchronizing method 审中-公开
标题翻译：用于信号的同步帧同步器，光盘驱动器，Informationsaufzeichungs-和再现设备和方法
公开(公告)号：EP1672910A1
公开(公告)日：2006-06-21
申请号：EP05027794.6
申请日：2005-12-19
申请人： NEC Electronics Corporation
发明人： Matsushima, Ko
IPC分类号： H04N5/073
CPC分类号： H04N21/4307 , H04N5/0736
摘要： To provide a frame synchronizer free of any loss of additional information added to frame data of an input video signal. An embodiment of the invention relates to a frame synchronizer for receiving a video signal having a first synchronization signal and frame data on a frame basis, writing the frame data to a memory on the frame basis in accordance with the first synchronization signal, and reading the frame data from the memory on the frame basis in accordance with a second synchronization signal of a frequency different from a frequency of the first synchronization signal to output the frame data, including: a synchronization signal generator generating the second synchronization signal having the frequency higher than a preset standard frequency. With such a configuration, it is possible to prevent the loss of the additional information added to the frame data in the input video data.
摘要翻译：免费提供的添加到帧的输入视频信号的数据的附加信息的任何损失的帧同步器。本发明的一个实施例涉及一种帧同步器，用于接收视频信号具有以帧为基础上的第一同步信号和帧数据，在雅舞的第一同步信号的帧数据写入到存储器中的帧的基础上，并读取该一个同步信号发生器，用于生成具有频率高于所述第二同步信号：从雅舞蹈的帧为基础的频率，从所述第一同步信号，以输出帧数据，包括的频率不同的第二同步信号上的存储器的帧数据预设标准频率。随着搜索的结构，能够防止添加到帧数据在输入视频数据中的附加信息的丢失。

4. 发明公开

EP1259065A3 Anordnung zum zeitrichtigen Kombinieren zweier Datenströme 审中-公开
标题翻译：安排时间精确组合两个数据流
公开(公告)号：EP1259065A3
公开(公告)日：2006-03-08
申请号：EP02100485.8
申请日：2002-05-14
申请人： Philips Intellectual Property & Standards GmbH , Koninklijke Philips Electronics N.V.
发明人： Peters, Matthias, Philips Corp. Intell. Prop. GmbH
IPC分类号： H04N5/45 , H04N5/067 , H04J3/06 , H04J3/08
CPC分类号： H04J3/08 , H04N5/0736
摘要： Eine erfindungsgemäße Anordnung zum zeitrichtigen Kombinieren eines ersten, kontinuierlichen, digitalen Datenstromes (V1), der ein Synchronsignal (S) enthält, mit einem zweiten, diskontinuierlichen digitalen Datenstrom (V2), weist die Anordnung zum Ausgleich dieser Diskontinuitäten auf:

ein erstes Verzögerungsglied (2), das den ersten Datenstrom (V1) um eine erste vorgegebene Zeitspanne verzögert,
ein zweites Verzögerungsglied (3), das das Synchronsignal (S) des ersten Datenstroms (V1) um eine zweite vorgegebene Zeitspanne verzögert,
einen Speicher (4), in den der zweite Datenstrom (V2) nach Maßgabe eines Write-Pointers (WP) geschrieben und aus dem er nach Maßgabe eines Read-Pointers (RP) gelesen wird, wobei der Write-Pointer (WP) durch jeden Impuls des unverzögerten Synchronsignals (S; WPR) des ersten Datenstromes (V1) und der Read-Pointer (RP) durch jeden Impuls (RPR) des mittels des zweiten Verzögerungsgliedes (3) verzögerten Synchronsignals des ersten Datenstromes (V1) zurückgesetzt wird, d.h. an den Anfang des Speichers (4) gesetzt wird, und
Mittel (6) zum Kombinieren oder Verarbeiten der Ausgangsdatenströme des ersten Verzögerungsglieds (2) und des Speichers (4),

wobei die erste Zeitspanne so gewählt ist, dass die Ausgangsdatenströme des ersten Verzögerungsglieds (2) und des Speichers (4) an den Mitteln (6) zum Kombinieren oder Verarbeiten in einer gewünschten zeitlichen Relation zueinander auftreten, und wobei die zweite Zeitspanne so gewählt ist, dass der Read-Pointer (RP) währende des Lesevorgangs aus dem Speicher (4) auch unter Berücksichtigung der in dem zweiten Datenstrom (V2) auftretenden Diskontinuitäten den Write-Pointer (WP) nicht einholt.

5. 发明公开

EP0732845A1 Procédé et dispositif de synchronisation d'un signal vidéo numérique 失效
标题翻译： Verfahren und Vorrichtung zur Synchronisierung eines digitalen Videosignals
公开(公告)号：EP0732845A1
公开(公告)日：1996-09-18
申请号：EP96400397.4
申请日：1996-02-26
申请人： THOMSON BROADCAST SYSTEMS
发明人： Portron, Isabelle , Demay, Alain , Le Queau, Philippe
IPC分类号： H04N5/073
CPC分类号： H04N21/2365 , H04N5/0736 , H04N7/56 , H04N21/4347
摘要： Le dispositif de synchronisation contient deux mémoires parallèles (16,17), une unité de détermination (23) des états d'écriture correspondant au déphasage entre le signal vidéo d'entrée (15) et le signal de synchronisation (19), une unité de gestion de l'écriture (24) qui détermine à chaque top d'écriture d'images la ou les mémoires d'écriture selon l'état d'écriture et la mémoire en cours de lecture. On modifie la façon d'écrire dans les mémoires automatiquement alors que la lecture des deux mémoires se fait séquentiellement et alternativement. L'invention permet de synchroniser des signaux vidéo par rapport à un signal de synchronisation avec une tolérance au glissement en fréquence pouvant aller jusqu'à 33 %.
摘要翻译：该方法涉及在存储器单元中形成两个并行存储器区域。这些都可以容纳视频图像。区域中的图像被顺序地和交替地读取。基于写入图像的开始和读取图像的开始之间的相位差来定义几个写入状态。州也是基于状况的改变。对于每次写入开始，确定一个状态。图像被写入一个或两个存储区域。开始写入和读取开始之间的行数被计数以确定相位差。

6. 发明公开

EP0201740A3 Video signal control circuit 失效
标题翻译：视频信号控制电路
公开(公告)号：EP0201740A3
公开(公告)日：1988-10-26
申请号：EP86105208
申请日：1986-04-15
申请人： SONY CORPORATION
发明人： Kubota, Tatsuya , Takanashi, Kenji
IPC分类号： H04N05/073
CPC分类号： H04N7/0137 , H04N5/0736 , H04N7/0105
摘要： A video signal control circuit having a memory (3), a write address generator (6) for generating a write address data supplied to the memory (3), by which an input digital video signal is written in the memory (3) at the address represented by the write address data, a read address generator (13) for generating a read address data supplied to the memory (3), by which a controlled digital video signal is read out from the memory (3) at the address represented by the read address data, an address comparator (16) for comparing the write and read address data and for generating a compared output pulse, a timing pulse generator (23, 27) for generating first and second timing pulses, each of which has a predetermined pulse duration, a still picture detector (40) supplied with the input digital video signal and for detecting whether the input digital video signal represents a still picture or not, a write address controller (21, 25, 30) supplied with the compared output pulse, the first timing pulse and the output of the still picture detector (40) and for controlling the write address generator (6) when the pulse duration of the compared output pulse is shorter than that of said first timing pulse and the still picture detector (40) detects that the input digital video signal represents a still picture, and a read address controller (22, 26, 34) supplied with the compared output pulse, the second timing pulse and the output of the still picture detector (40) and for controlling the read address generator (13) when the pulse duration of the compared output pulse is shorter than that of the second timing pulse and the still picture detector means (40) detects that the input digital video signal represents a still picture.

7. 发明公开

EP0025364A2 Digital television video signal storage system 失效
标题翻译： Speichersystemfürein digitales Fernsehvideosignal。
公开(公告)号：EP0025364A2
公开(公告)日：1981-03-18
申请号：EP80303194.7
申请日：1980-09-11
申请人： NEC CORPORATION
发明人： Kashigi, Kazuo c/o Nippon Electric Co, Ltd , Kouyama, Toshitake c/o Nippon Electric Co, Ltd
IPC分类号： H04N5/06
CPC分类号： H04N5/0736 , H04N5/907
摘要： A storage system for 625/50 PAL colour television signals sampled at 3 times colour subcarrier frequency (eg in a frame synchronizer) has a memory unit (6) composed of 10 memory cards. A burst controlled oscillator (11) derives clock pulses (12) and subcarrier frequency pulses (25). Write address generator (13) includes separation circuits (26, 28, 30) for providing vertical and horizontal pulses which control a vertical address generator (34) and a memory card selecting counter (36). The same address code can be used for 24 different samples, so that a line of 783 samples requires 26 addresses. If a vertical/horizontal address system were to be employed then 625 lines of 26 addresses would be required or 10 pulse 5 = 15 address bits. By transforming the addresses from the vertical address generator this can be reduced to 14 bits (ie the storage halved). A multiplier (41) multiplies the vertical address by a factor of 26 to give start address data which is loaded into a write memory address counter (43) at the start of each line. This counter is incremented once for each cycle of the card selecting counter (36). The read circuitry is similar.
摘要翻译：用于以3倍彩色副载波频率采样的625/50 PAL彩色电视信号的存储系统（例如在帧同步器中）具有由10个存储卡组成的存储单元（6）。突发控制振荡器（11）导出时钟脉冲（12）和子载波频率脉冲（25）。写地址发生器（13）包括用于提供控制垂直地址发生器（34）和存储卡选择计数器（36）的垂直和水平脉冲的分离电路（26,28,30）。相同的地址码可用于24个不同的样本，因此783个样本的一行需要26个地址。如果要使用垂直/水平地址系统，则需要625行26个地址，或者10个脉冲5 = 15个地址位。通过从垂直地址生成器转换地址，可将其减少到14位（即存储量减半）。乘法器（41）将垂直地址乘以因子26，以在每行开始时提供加载到写存储器地址计数器（43）中的起始地址数据。该计数器对于卡选择计数器（36）的每个周期递增一次。读取电路类似。

8. 发明公开

EP0017636A1 A method and a device for synchronizing a digital memory with an existing TV-system 失效
标题翻译：用于与现有的电视系统中同步数字存储器的方法和装置。
公开(公告)号：EP0017636A1
公开(公告)日：1980-10-15
申请号：EP80850037.5
申请日：1980-03-25
申请人： GLOBE COMPUTERS AB
发明人： Wärn, Stefan
IPC分类号： H04N5/22
CPC分类号： H04N5/0736
摘要： The aim of the present invention is to make it possible to synchronize a digital memory (8) with an existing TV-system, in which a TV-picture is transmitted with video interlace. According to the invention a corrected field synchronizing pulse (B2) is formed by means of a composite sync signal (S) of the TV-system, which pulse (B2), in spite of the video interlace, always appears at the starting point of a line and by means of which a part in an address counter (6) for the memory associated with vertical addressing of the memory is reset to a starting position at the starting point of each picture field. The address counter is stepped for addressing purposes by means of a clock signal from a main oscillator (5). the frequency of which is controlled in response to a comparison between a line synchronizing signal (L1) derived from the composite sync signal and hne frequency signals (L2, L3) supplied from the address counter.

9. 发明公开

EP3404649A1 VIDEO OUTPUT APPARATUS, CONVERSION APPARATUS, VIDEO OUTPUT METHOD, AND CONVERSION METHOD 有权
公开(公告)号：EP3404649A1
公开(公告)日：2018-11-21
申请号：EP18168888.8
申请日：2018-04-24
申请人： Sony Interactive Entertainment Inc.
发明人： KAWAMURA, Yuji , YANABA, Koji , YOSHIMURA, Kousuke
IPC分类号： G09G5/399 , H04N7/01
CPC分类号： H04N7/01 , G09G5/005 , G09G5/399 , G09G2370/12 , H04N5/0736 , H04N7/0105 , H04N7/0127 , H04N7/013
摘要： A video output apparatus that outputs video data in a first format to a conversion apparatus that converts and outputs the received data in the first format into data in a second format. The conversion apparatus sequentially outputs a blank signal, a vertical synchronization signal, and a blank signal. The video output apparatus includes a frame image data output unit that outputs the first frame image data to the conversion apparatus, a blank signal output unit that outputs a blank signal to the conversion apparatus, and a trigger signal output unit that outputs, to the conversion apparatus, a trigger signal to be converted into a vertical synchronization signal by the conversion apparatus.

10. 发明公开

EP1559265A2 A SYSTEM AND METHOD FOR DETERMINING LIP SYNCHRONIZATION BETWEEN AUDIO AND VIDEO IN A DIGITIZED ENVIRONMENT USING BUFFER CALCULATION 审中-公开
标题翻译：系统和方法用于确定之间的音频和视频唇音同步以数字化的环境中使用BUFFER计算
公开(公告)号：EP1559265A2
公开(公告)日：2005-08-03
申请号：EP03778011.1
申请日：2003-10-31
申请人： Thomson Licensing S.A.
发明人： JOHNSON, Devon, Matthew , JUNKERSFELD, Phillip, Aaron
IPC分类号： H04N1/00
CPC分类号： H04N21/4341 , H04N5/04 , H04N5/0736 , H04N5/4401 , H04N21/23406 , H04N21/2368 , H04N21/4305 , H04N21/44004
摘要： The disclosed embodiments relate to a system (23) and method (400) for maintaining synchronization between a video signal (29) and an audio signal (31) that are processed using clocks that are locked. The system (23) may comprise a component (34) that determines at least one initial level of a buffer, a component (34) that determines at least one current level of the buffer, and a component (34) that determines an amount of drift by comparing the at least one initial level of the buffer to the at least one current level of the buffer and adjusts the clocks to maintain the initial midpoint level of the buffer if the amount of drift reaches a threshold level.

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