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1. 发明授权

EP4004657B1 FLEXIBLE LATENCY-MINIMIZED DELIVERY AND MANAGEMENT OF DISPARATE-RATE DATA STREAMS AND SUB-STREAMS FOR PROCESSING 有权
公开(公告)号：EP4004657B1
公开(公告)日：2024-09-04
申请号：EP20754092.3
申请日：2020-07-22
IPC分类号： G05B19/042 , H03M1/06
CPC分类号： H03M1/06 , G05B19/042

2. 发明授权

EP2779462B1 Clock signal error correction in a digital-to-analog converter 有权
公开(公告)号：EP2779462B1
公开(公告)日：2018-10-17
申请号：EP14159962.1
申请日：2014-03-14
申请人： Analog Devices, Inc.
发明人： Schafferer, Bernd , Lai, Ping Wing , He, Quirong
IPC分类号： H03M1/06 , G06F1/04 , H03M1/10 , H03M1/74 , H03M1/66
CPC分类号： H03M1/1009 , G06F1/04 , H03M1/06 , H03M1/0678 , H03M1/66 , H03M1/742
摘要： In an example, there is disclosed herein a digital-to-analog converter (DAC) including a correction circuit for a clock, including a differential clock. Error correction may take place within the DAC core, by means of replica cells that are substantially similar to conversion cells. Rather than contributing their output to the converted signal, the replica cells may be configured to provide a feedback signal to a clock receiver with information for correcting the clock signal. The feedback signal may be operable to correct errors, for example, in duty cycle and crosspoint, as measured at the DAC core.

3. 发明公开

EP3217561A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：EP3217561A1
公开(公告)日：2017-09-13
申请号：EP17159283.5
申请日：2017-03-06
申请人： Renesas Electronics Corporation
发明人： FUNATO, Yoshihiro , MORIMOTO, Yasuo
IPC分类号： H03M1/06 , H03M1/46
CPC分类号： H03M1/466 , H03M1/06 , H03M1/0695 , H03M1/468
摘要： A semiconductor device according to the present invention has a capacitance DAC (Digital-to-Analog Converter) circuit and a comparator.
The capacitance DAC circuit includes: first capacitors to which input signals are given and each of which has a capacitance value corresponding to a weight of a bit to be converted; and second capacitors to which common voltages are given and whose sum of capacitance values is equivalent to that of the first capacitors. Further, the second capacitors include: a redundant bit capacitor having a capacitance value corresponding to a weight of a redundant bit; and adjustment capacitors each having a capacitance value obtained by subtracting the capacitance value of the redundant bit capacitor from the sum of the capacitance values of the second capacitors.
摘要翻译：根据本发明的半导体器件具有电容DAC（数字 - 模拟转换器）电路和比较器。该电容DAC电路包括：第一电容器，其被给予输入信号并且其中的每一个具有与要被转换的比特的权重相对应的电容值; 以及被施加公共电压并且其电容值之和等于第一电容器的电容值的第二电容器。此外，第二电容器包括：具有与冗余位的权重对应的电容值的冗余位电容器; 以及调整电容器，每个调整电容器具有通过从第二电容器的电容值的总和中减去冗余位电容器的电容值而获得的电容值。

4. 发明公开

EP2658130A1 DIGITAL/ANALOG CONVERTER AND METHOD FOR CONTROLLING SAME 审中-公开
标题翻译： VERFAHREN ZU SEINER STEUERUNG数字模拟服务器
公开(公告)号：EP2658130A1
公开(公告)日：2013-10-30
申请号：EP12858683.1
申请日：2012-10-31
申请人： Asahi Kasei Microdevices Corporation
发明人： NAKAMOTO, Seiko , NAKANISHI, Junya
IPC分类号： H03M1/74
CPC分类号： H03M1/806 , H03M1/06 , H03M1/804
摘要： A digital-analog converter circuit includes sampling capacitive elements (111, 112, ..., 11N) of which one ends are to be electrically connected to and disconnected from input terminals (D1, D2, ..., DN), to which digital signals are input, via a switch unit (SWu10), an operational amplifier (501), a switch (301) capable of electrically connecting and disconnecting the other ends of the sampling capacitive elements (111, 112, ..., 11N) and an inverting input terminal of the operational amplifier (501), and a switch unit (SWu40) that is disposed between nodes between the switch unit (SWu10) and the sampling capacitive elements (111, 112, ..., 11N) and the output terminal of the operational amplifier (501) and capable of connecting and disconnecting them. An on-resistance value of a MOS transistor included in the switch (301) is set to be larger than an on-resistance value of a MOS transistor included in the switch unit (SWu40).
摘要翻译：数模转换器电路包括对其一端电连接到输入端（D1，D2，...，DN）并与其断开的电容元件（111,112，...，11N）进行采样，其中数字信号经由开关单元（SWu10），运算放大器（501），能够电连接和断开取样电容元件（111,112，...，11N）的另一端的开关（301）输入，和运算放大器（501）的反相输入端子和设置在开关单元（SWu10）和采样电容元件（111,112，...，11N）之间的节点之间的开关单元（SWu40）和运算放大器（501）的输出端子，并且能够连接和断开它们。包括在开关（301）中的MOS晶体管的导通电阻值被设置为大于包括在开关单元（SWu40）中的MOS晶体管的导通电阻值。

5. 发明授权

EP1769582B1 CURRENT PARKING RETURN TO ZERO DIGITAL-TO-ANALOG CONVERTER 有权
标题翻译：电力公园返回到零，数字/模拟转换
公开(公告)号：EP1769582B1
公开(公告)日：2011-05-11
申请号：EP05727756.8
申请日：2005-03-15
申请人： Northrop Grumman Systems Corporation
发明人： HARBERTS, Harry, S. , HINRICHS, Jeffrey, M.
IPC分类号： H03M1/06
CPC分类号： H03M1/06 , H03K17/04113 , H03K17/16 , H03M1/742 , H03M3/348 , H03M3/502
摘要： A digital-to-analog converter having a differential signal path, and a current parking circuit that is independent of the signal path, thereby avoiding a source of imbalance that caused output anomalies in conventional digital-to-analog circuitry. In one embodiment of the invention, a pair of diodes in the current parking circuit are connected through their own independent load resistors to a voltage source. In another embodiment, a single diode is used instead of the pair of diodes, and in a third embodiment the current parking circuit comprises a single load resistor connected to the voltage source, and no diodes at all.

6. 发明公开

EP2246985A1 Complex-admittance digital-to-analog converter 失效转让
标题翻译： Digital-Analog-Umsetzerfürkomplexe Leitwerte
公开(公告)号：EP2246985A1
公开(公告)日：2010-11-03
申请号：EP10004454.4
申请日：2010-04-27
申请人： Linear Technology Corporation
发明人： Thomas, Andrew Joseph , Sousa, Joseph Luis
IPC分类号： H03M1/80 , H03M1/06
CPC分类号： H03M1/80 , H03M1/06
摘要： A circuit includes a digital-to-analog converter configured to produce an analog output signal (1) proportional to a reference signal and (2) as a function of a digital input signal. The converter comprises a plurality of non-trivially complex admittances configured so that each non-trivially complex admittance can be selectively switched as a function of the digital input signal so as to be coupled between a reference terminal configured to receive a reference signal and an output terminal. The method comprises selectively switching non-trivially complex admittances as a function of the digital signal between a reference terminal and an output terminal.
摘要翻译：电路包括被配置为产生与参考信号成比例的模拟输出信号（1）和（2）作为数字输入信号的函数的数模转换器。转换器包括多个非常复杂的导纳，其被配置为使得可以根据数字输入信号选择性地切换每个非平凡复杂的导纳，以便耦合在被配置为接收参考信号的参考端和输出终奌站。该方法包括根据参考端和输出端之间的数字信号选择性地切换非常复杂的导纳。

7. 发明公开

EP1901273A3 Data driver and driving method of organic light emitting display device using the same 审中-公开
标题翻译：数据驱动器和有机发光显示装置，使得驱动方法
公开(公告)号：EP1901273A3
公开(公告)日：2009-03-18
申请号：EP06256268.1
申请日：2006-12-08
申请人： Samsung Mobile Display Co., Ltd.
发明人： Kim, Do Youb, Legal & IP Team , Choi, Sang-Moo, Legal & IP Team , Park, Yong-Sung, Legal & IP Team
IPC分类号： G09G3/32
CPC分类号： H03M1/06 , G09G3/3291 , G09G2310/027 , H03M1/682
摘要： A data driver capable of generating data signals with desired voltage values. The data driver includes a first digital-analog converter including a plurality of first switches, the first digital-analog converter selecting two reference voltages from among a plurality of reference voltages by turning on two of the first switches corresponding to high level bits of data; and a second digital-analog converter for dividing the two reference voltages into a plurality of voltages and for supplying any one of the two reference voltages and the divided voltages corresponding to low level bits of the data as a data signal to an output terminal, wherein the second digital-analog converter includes a transistor turned on by a bias voltage to compensate for a turn-on resistance of the two of the first switches.

8. 发明授权

EP0721269B1 Integrierte CMOS-Schaltung 失效
标题翻译： CMOS集成电路
公开(公告)号：EP0721269B1
公开(公告)日：2008-08-20
申请号：EP95119724.3
申请日：1995-12-14
申请人： Naxos Data LLC
发明人： Banniza, Thomas , Preisach, Helmut
IPC分类号： H04L25/02
CPC分类号： H04L25/0298 , H01L2924/0002 , H03H11/28 , H03M1/06 , H03M1/48 , H03M1/742 , H01L2924/00

9. 发明公开

EP0931212A1 VERFAHREN ZUR ERMITTLUNG VON SEGMENTZEITEN 失效
标题翻译：片段时间计算书
公开(公告)号：EP0931212A1
公开(公告)日：1999-07-28
申请号：EP98944999.0
申请日：1998-07-16
申请人： ROBERT BOSCH GMBH
发明人： LANG, Tobias , ZIMMERMANN, Michael
IPC分类号： F02D45 , F02D41 , H03M1
CPC分类号： H03M1/06 , F02D41/009 , H03M1/143
摘要： The invention relates to a method for determining segment times which can be implemented for internal combustion engines when only approximate camshaft angle information is available, e.g. when there is a defect in the crankshaft increment sensor and the determined segement times are too imprecise to regulate the internal combustion engine in a reliable manner. Accelerations which can be triggered through ignitions are subsequently determined. Said accelerations are converted into coefficients and used to correct segment times.

10. 发明公开

EP0325378A3 Digital-to-analog converter 失效
标题翻译：数字到模拟转换器
公开(公告)号：EP0325378A3
公开(公告)日：1992-02-26
申请号：EP89300319.4
申请日：1989-01-13
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Linz, Alfredo R. , Peterson, Joe W. , Nair, Velayudhan Vijayakumaran
IPC分类号： H03M1/78 , H03M1/06
CPC分类号： H03M1/06 , H03M1/68 , H03M1/785 , H03M1/808
摘要： A digital-to-analog converter network for converting a digital signal having a plurality of binary bits into an analog output signal includes an R-2R ladder array (8a), a reference current source (IREF), a plurality of switches (S1, S2, ...S9) associated with ladder sections of the ladder array (8a), and an operational amplifier (14). An equalization circuit (17) is operatively coupled to the inverting input of the operational amplifier (14) for selectively switching in a code-dependent impedance so that the effective output impedance of the ladder array (8a) remains substantially constant with binary codes of the digital input signal.

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