专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP2194645A3 Low-power relaxation oscillator and RFID tag using the same 审中-公开
标题翻译：低功耗张弛振荡器和RFID标签，以便
公开(公告)号：EP2194645A3
公开(公告)日：2012-07-18
申请号：EP09172282.7
申请日：2009-10-06
申请人： Electronics and Telecommunications Research Institute
发明人： Kang, Tae Young , Park, Kyung Hwan , Hyun, Seok Bong , Kang, Tae Wook , Kim, Kyung Soo , Kim, Sung Eun , Kim, Jung Bum , Myoung, Hey Jin , Park, Hyung II , Lim, In Gi , Choi, Byoung Gun , Hyoung, Chang Hee , Hwang, Jung Hwan , Kang, Sung Weon
IPC分类号： H03K3/03 , H03K3/0231
CPC分类号： H03K3/03 , H03K3/0231
摘要： There is provided a low-power relaxation oscillator (100). The low-power relaxation oscillator may include: a constant current generation unit (110) generating a current having a predetermined magnitude; a current varying unit (120) controlling the current generated from the constant current generation unit according to a clock control signal (CT1,CT2,CT3,CT4) to output the controlled current; a first controller (131) and a second controller (132) connected in parallel with output terminals of the current varying unit and passing or interrupting the current supplied from the current varying unit; a PMOS charging/discharging unit (140) arranged between an output terminal of the first controller (N1) and an output terminal of the second controller (N2); a first comparator (151) and a second comparator (152) connected to both ends of the PMOS charging/discharging unit (140), respectively, and each outputting a high or low level voltage upon receiving voltage charged in the PMOS charging/discharging unit (140); and a latch circuit (160) delaying the voltages output from the first and second comparators to output, oscillation signals (V 01 ,V 02 ).

2. 发明公开

EP1855380A1 CURRENT CONTROLLED OSCILLATOR 有权
标题翻译： STROMGESTEUERTER OSZILLATOR
公开(公告)号：EP1855380A1
公开(公告)日：2007-11-14
申请号：EP05719658.6
申请日：2005-02-28
申请人： Fujitsu Ltd.
发明人： YAMAZAKI, Daisuke c/o FUJITSU LIMITED, , RADECKI, Andrzej Room 303
IPC分类号： H03K3/027
CPC分类号： H03K3/027 , H03K3/03 , H03K4/502
摘要： Widening the frequency range without increasing the power consumption.
Current circuits (1a) and (1b) output charge current based on control current. Capacitors (C1) and (C2) are provided in association with the current circuits (1a) and (1b) and store the charge current. Discharge transistors (M1) and (M3) are provided in association with the capacitors (C1) and (C2) and cause the capacitors (C1) and (C2) to discharge electric charge. On-off transistors are connected between the current circuits (1a) and (1b) and the capacitors (C1) and (C2) and open or close the paths between the current circuits (1a) and (1b) and the capacitors (C1) and (C2) in accordance with the voltages across the capacitors (C1) and (C2). Signal output transistors (M5) and (M6) have their gates connected between the current circuits (1a) and (1b) and the on-off transistors (M2) and (M4) and output signals to a flip-flop (2) in accordance with the charge current. The flip-flop (2) drives the discharge transistors (M1) and (M3) alternately in accordance with the signals.
摘要翻译：扩大频率范围而不增加功耗。电流电路（1a）和（1b）根据控制电流输出充电电流。与电流电路（1a）和（1b）相关联地提供电容器（C1）和（C2），并存储充电电流。与电容器（C1）和（C2）相关联地设置放电晶体管（M1）和（M3），并使电容器（C1）和（C2）放电。导通晶体管连接在电流电路（1a）和（1b）与电容器（C1）和（C2）之间，并打开或关闭电流电路（1a）和（1b）与电容器（C1）之间的路径，和（C2）根据电容器（C1）和（C2）两端的电压。信号输出晶体管（M5）和（M6）的栅极连接在电流电路（1a）和（1b）与开 - 关晶体管（M2）和（M4）之间，并将输出信号输出到触发器按照充电电流。触发器（2）根据信号交替地驱动放电晶体管（M1）和（M3）。

3. 发明公开

EP1569338A1 Voltage controlled oscillator 失效
标题翻译：压控振荡器
公开(公告)号：EP1569338A1
公开(公告)日：2005-08-31
申请号：EP04106956.8
申请日：1997-09-05
申请人： Oki Electric Industry Company, Limited
发明人： Takahiro, Kamei
IPC分类号： H03K3/03
CPC分类号： H03K3/0322 , H03K3/0231 , H03K3/03
摘要： The voltage controlled oscillator comprising a ring oscillator outputs an oscillating signal of which the duty cycle is almost 50% in spite of the high frequency. Each of the delay inverting circuits (10,20,30) in the ring oscillator varies the output signal from the "L" level to the "H" level for the constant delay time tr when the input signal varies the "H" level to the "L" level. It also varies the output signal from the "H" level to the "L" level for the variable delay time tf in response to the delay control voltage Vc when the input signal varies the "L" level to the "H" level. The output signal from the ring oscillator comprising the delay inverting circuits (10,20,30) is applied to another delay inverting circuit (40). The another delay inverting circuit responses at the constant delay time tr when the input signal varies the "H" level to the "L" level, and responses at the delay time tf/2 in accordance with the delay control voltage Vc when the input signal varies the "L" level to the "H" level. As a result, the another delay inverting circuit outputs an oscillating signal of which the duty cycle is almost 50%.
摘要翻译：包括环形振荡器的压控振荡器输出尽管频率高但占空比几乎为50％的振荡信号。当输入信号将“H”电平改变为“1”时，环形振荡器中的每个延迟反相电路（10,20,30）将输出信号从“L”电平变为“H”电平持续恒定延迟时间tr “L”级。响应于当输入信号将“L”电平变为“H”电平时的延迟控制电压Vc，它还将可变延迟时间tf的输出信号从“H”电平变为“L”电平。来自包括延迟反相电路（10,20,30）的环形振荡器的输出信号被施加到另一个延迟反相电路（40）。当输入信号将“H”电平变为“L”电平时，另一延迟倒相电路在恒定延迟时间tr处响应，并且当输入信号时根据延迟控制电压Vc在延迟时间tf / 2处响应将“L”电平变为“H”电平。结果，另一个延迟反相电路输出占空比几乎为50％的振荡信号。

4. 发明公开

EP1543407A2 SWITCHING ELECTRONIC CIRCUIT FOR RANDOM NUMBER GENERATION 有权
标题翻译：采样电路兰德GENERATION
公开(公告)号：EP1543407A2
公开(公告)日：2005-06-22
申请号：EP03771230.4
申请日：2003-07-14
申请人： Koninklijke Philips Electronics N.V.
发明人： HARS, Laszlo
IPC分类号： G06F7/58
CPC分类号： H03K3/84 , H03K3/03
摘要： A physical random number generator (10) has a bi-stable latch (40) that operates to latch a random number bit (RNB) in response to a reception of a voltage oscillating signal (VOS). When a switching device (20) is in a first operating state, the bi-stable latch (40) is deactivated and an oscillator (30) is activated to generate one or more unpredictable voltage oscillation signals (VOS), which may provoke the bi-stable latch (40) into a metastable state upon an activation of the bi-stable latch (40). When the switching device (20) is in a second operating state, the oscillator (30) is deactivated and the bi-stable latch (40) is activated to latch a random number bit (RNB) as a function of the unpredictable voltage oscillation signals (VOS), the randomness of the random number bit (RNB) being enhanced by any provoking of the bi-stable latch (40) into the metastable state by the voltage oscillating signal(s) (VOS).

5. 发明授权

EP1120911B1 Voltage-controlled oscillator 有权
公开(公告)号：EP1120911B1
公开(公告)日：2004-05-26
申请号：EP01101808.2
申请日：2001-01-26
申请人： NEC Electronics Corporation
发明人： Soda, Masaaki, c/o NEC Corporation
IPC分类号： H03K3/0231
CPC分类号： H03K3/03 , H03K3/0231 , H03K3/0322

6. 发明公开

EP1143605A2 An Oscillator circuit 有权
标题翻译： Eine Oszillatorschaltung
公开(公告)号：EP1143605A2
公开(公告)日：2001-10-10
申请号：EP01302164.7
申请日：2001-03-09
申请人： Texas Instruments Limited , Texas Instruments Incorporated
发明人： Harwood, Michael
IPC分类号： H03B5/32
CPC分类号： H03B5/364 , H03K3/011 , H03K3/03 , H03K3/354
摘要： An oscillator has a PMOS and a NMOS transistor connected in series across a power supply. The output at the node between them is fed back through the gate of the NMOS transistor via a crystal feedback circuit. The voltage applied to the gate of the PMOS transistor is set by a biasing circuit to achieve a bias for the NMOS transistor of halfway between the threshold voltage of the NMOS transistor and the positive power supply. To do this, that voltage level is derived from a voltage divider connected across the power supply, comprising two equal resistors and a NMOS transistor, having its gate connected to its drain, and is applied to the gate of a third NMOS transistor which is connected in series with another PMOS transistor across the power supply. The bias for both PMOS transistors is provided by an operational amplifier which compares the gate voltage of the third NMOS transistor to its source voltage. An advantage of the circuit is that it operates at low power supply voltages.
摘要翻译：振荡器具有在电源上串联连接的PMOS和NMOS晶体管。它们之间的节点处的输出经由晶体反馈电路经由NMOS晶体管的栅极反馈。施加到PMOS晶体管的栅极的电压由偏置电路设置，以在NMOS晶体管的阈值电压和正电源之间实现NMOS晶体管的偏置。为了做到这一点，该电压电平是从连接在电源上的分压器导出的，包括两个相等的电阻器和NMOS晶体管，其栅极连接到其漏极，并被施加到连接到第三个NMOS晶体管的栅极与电源上的另一个PMOS晶体管串联。两个PMOS晶体管的偏置由运算放大器提供，运算放大器将第三NMOS晶体管的栅极电压与其源极电压进行比较。该电路的优点是它在低电源电压下工作。

7. 发明公开

EP1092266A1 A TUNABLE DIGITAL OSCILLATOR CIRCUIT AND METHOD FOR PRODUCING CLOCK SIGNALS OF DIFFERENT FREQUENCIES 审中-公开
标题翻译：数字调谐振荡器电路和方法产生时钟信号频率不同
公开(公告)号：EP1092266A1
公开(公告)日：2001-04-18
申请号：EP99927122.4
申请日：1999-05-28
申请人： S3 Incorporated
发明人： FURMAN, Elliot
IPC分类号： H03K5/13
CPC分类号： H03K3/03 , H03K5/131
摘要： A tunable digital oscillator circuit comprising a first dual-clock pulse generator (202), a second dual-clock pulse generator (204), a run controller (104), a stop controller (106) and a decoder (108). The first and second dual-clock pulse generators are coupled in a cascaded manner with the output of the first dual-clock pulse generator provided as an input to the second dual-clock pulse generator. Each of the first and second dual-clock pulse generators is preferably tunable, in that, they can output one clock signal from a predetermined number of frequencies. The run controller is preferably coupled to receive a start signal and the output of the second dual-clock pulse generator. The run controller provides the input to begin and maintain the first and second dual-clock pulse generators in the state of generating a clock signal. The stop controller is coupled to receive a clock signal from the first dual-clock pulse generator, and a stop signal. The tunable digital oscillator circuit can start or stop the clock within two clock cycles. The decoder receives a period select signal and provides a control signal to the first and second dual-clock pulse generators to select one of a predetermined number of frequencies for the clock signal.

8. 发明授权

EP0773626B1 Oscillator for oscillating stable frequency formed on a semiconductor substrate 失效
标题翻译：在半导体基板振荡器稳定的频率产生
公开(公告)号：EP0773626B1
公开(公告)日：2000-12-06
申请号：EP96115182.6
申请日：1996-09-20
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Park, Hyung-Sik
IPC分类号： H03L1/02 , H03K3/011 , H03K3/03
CPC分类号： H03K3/03 , H03K3/011

9. 发明公开

EP1049256A1 Low supply voltage oscillator circuit, particularly of the CMOS type 审中-公开
标题翻译： Oszillatorschaltung，insbesondere vom CMOS-Typ，mit niedriger Versorgungsspannung
公开(公告)号：EP1049256A1
公开(公告)日：2000-11-02
申请号：EP99830260.8
申请日：1999-04-30
申请人： STMicroelectronics S.r.l.
发明人： Pulvirenti, Francesco
IPC分类号： H03K3/354 , H03K3/03
CPC分类号： H03K3/354 , H03K3/03
摘要： A low supply voltage oscillator circuit (4) of the type which comprises at least one capacitor (C1,C2) to be controlled, connected between first (VDD) and second (GND) voltage references, and a circuit for charging and discharging the capacitor to be controlled.
The oscillator circuit (4) of the invention comprises at least first (A) and second (B) stages having symmetrical structures in a mirror-image configuration and being connected between the first voltage reference (VDD) and the second voltage reference (GND) and connected together through a memory element (FF) and respective primary switches (N3,N4) for alternately charging in a controlled fashion said capacitors (C1,C2).
摘要翻译：一种低电源电压振荡器电路（4），包括至少一个待控制的电容器（C1，C2），连接在第一（VDD）和第二（GND）电压基准之间，以及用于对电容器充电和放电的电路被控制。本发明的振荡器电路（4）至少包括第一（A）和第二（B）级，其具有镜像配置中的对称结构，并连接在第一参考电压（VDD）和第二参考电压（GND）之间。并且通过存储元件（FF）和相应的初级开关（N3，N4）连接在一起，用于以受控的方式交替地充电所述电容器（C1，C2）。

10. 发明公开

EP0806840A3 Radio frequency transceiver and subassemblies thereof 失效
标题翻译：无线电接收器和模块
公开(公告)号：EP0806840A3
公开(公告)日：2000-04-12
申请号：EP97104279.1
申请日：1997-03-13
申请人： SYMBOL TECHNOLOGIES, INC.
发明人： Vu, Hoai X. , Vu, Toan
IPC分类号： H04B1/00 , H04B1/30 , H04B1/40
CPC分类号： H03K3/03 , H03G3/3089 , H03K3/0322 , H04B1/44
摘要： Thus, a transceiver having a transmitter section and a receiver section is provided. The transmitter section includes a modulator to superimpose information, i.e., data, onto the amplitude of a suitable carrier signal, such as a microwave frequency carrier signal. The receiver section receives data carried by the carrier frequency signal and, in a heterodyning system, downconverts the received signal to a suitable intermediate frequency signal. The modulator and the downconverter are formed on a single semiconductor body, or chip of silicon. The receiver section is adapted to receive over a predetermined overall bandwidth signals having carrier frequencies within a plurality of frequency channels, each one of the channels having a predetermined channel bandwidth; and, a sampler for sampling such received signals at a sampling frequency less twice the predetermined overall bandwidth. The sampling frequency is selected to convert the carrier frequency of a signal within a selected one of the frequency channels to a frequency within a predetermined intermediate frequency and to convert the carrier frequencies of signals of the un-selected one of the frequency channels to frequencies other than the predetermined intermediate frequency. The downconverted signals are converted into corresponding digital signals. A demodulator includes a Hilbert-Transform-pair filter section. The receiver includes: a first automatic gain control circuit (AGC) and is responsive to an output of the digital signal processor, for adjusting the gain of the AGC circuit in accordance with the output of the digital signal processor; and, a second AGC circuit fed by the digital signals and the output of the digital signal processor, for adjusting the gain of the magnitude of the digital signals in accordance with the output of the digital signal processor.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式