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1. 发明公开

EP1089344A3 Insulated gate field effect transistor and method of fabricating the same 审中-公开
标题翻译：场效应晶体管用绝缘栅和制备过程
公开(公告)号：EP1089344A3
公开(公告)日：2003-07-23
申请号：EP00307920.9
申请日：2000-09-13
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Mizuki, Ono, Intellectual Property Division
IPC分类号： H01L29/78 , H01L21/336 , H01L29/51 , H01L21/28 , H01L29/423
CPC分类号： H01L29/4983 , H01L21/28035 , H01L21/28114 , H01L21/28194 , H01L21/28202 , H01L29/4991 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66575 , H01L29/66659
摘要： A field-effect transistor comprises a semiconductor substrate (101), a gate insulation film (111, 109') formed selectively on the semiconductor substrate (101), a gate electrode (106) formed on the gate insulation film (111, 109'), source/drain regions (107) formed in surface portions of the semiconductor substrate (101) along mutually opposed side surfaces of the gate electrode (106), the source/drain regions (107) having opposed end portions located immediately below the gate electrode (106), each of the opposed end portions having an overlapping region which overlaps the gate electrode (106), and a channel region (104) formed in a surface portion of the semiconductor substrate (101), which is sandwiched between the opposed source/drain regions (107). That portion (109') of the gate insulation film (111, 109'), which is located at the overlapping region where at least one of the source/drain regions (107) overlaps the gate electrode (106), has a lower dielectric constant than that portion (111) of the gate insulation film (111, 109'), which is located on the channel region (104). Thereby, a short channel effect can be fully suppressed, and a high-speed operation can be realized.
摘要翻译：一种场效应晶体管包括：半导体衬底（101），栅绝缘膜（111，109“）形成在栅极绝缘膜的半导体衬底（101）上选择性地形成，栅电极（106）（111，109” 在沿着栅电极（106）的相互相对的侧表面的半导体衬底（101）的表面部分而形成），源/漏区（107），源极/漏极区（107），其具有相对紧位于栅极下面的端部电极（106），每一个都具有在重叠的区域，该区域与栅电极重叠（106）和在所述半导体衬底（101）的表面部分中形成的沟道区（104）的相对的末端部分中，所有这一切都被夹在对置之间源/漏区（107）。 “（，其位于所述重叠区域中的源/漏区，其中至少一个（107）在栅绝缘膜111，109）的该部分（109）”与栅电极重叠（106）具有较低的介电比，其位于所述沟道区域（104）的栅极绝缘膜 - （111，109“），在所有的部分（111）是恒定的。由此，短沟道效应可以完全抑制，并且一个高速运算可以实现。

2. 发明公开

EP3326206A1 TRANSISTOR WITH AIRGAP SPACER 有权
公开(公告)号：EP3326206A1
公开(公告)日：2018-05-30
申请号：EP15899048.1
申请日：2015-07-17
申请人： Intel Corporation
发明人： LEE, Chen-Guan , PARK, Joodong , LIU, En-Shao , CASSIDY-COMFORT, Everett S. , HAFEZ, Walid M. , JAN, Chia-Hong
IPC分类号： H01L29/49 , H01L21/764 , H01L21/768 , H01L29/66
CPC分类号： H01L29/4991 , H01L21/764 , H01L21/7682 , H01L21/76897 , H01L29/66545 , H01L29/78
摘要： A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.

3. 发明公开

EP3203501A3 NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：非易失性存储器装置及其制造方法
公开(公告)号：EP3203501A3
公开(公告)日：2017-11-01
申请号：EP17152661.9
申请日：2017-01-23
申请人： Semiconductor Manufacturing International Corporation (Shanghai) , Semiconductor Manufacturing International Corporation (Beijing)
发明人： SONG, Changgeng
IPC分类号： H01L21/28 , H01L29/423 , H01L21/764 , H01L27/11524 , H01L27/11529 , H01L27/11536 , H01L27/11539 , H01L27/11541 , H01L27/11543
CPC分类号： H01L27/11543 , H01L21/28273 , H01L21/28282 , H01L21/764 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11536 , H01L27/11539 , H01L27/11541 , H01L27/11568 , H01L27/1157 , H01L27/11573 , H01L29/0657 , H01L29/42324 , H01L29/4234 , H01L29/4991
摘要： A method for manufacturing a semiconductor device includes providing a substrate structure having an active region, a gate insulating layer, a charge storage layer, a gate dielectric layer, and a gate electrode layer sequentially formed on the active region. The method also includes forming a patterned metal layer on the substrate structure, removing a respective portion of the gate electrode layer, the gate dielectric layer, the charge storage layer using the patterned metal gate electrode layer as a mask to form multiple gate structures separated from each other by a space. The gate structures each include a stack containing a second portion of the charge storage layer, the gate dielectric layer, the gate electrode layer, and one of the gate lines. The method further includes forming an interlayer dielectric layer on a surface of the gate structures stretching over the space while forming an air gap in the space.
摘要翻译：一种用于制造半导体器件的方法包括提供具有依次形成在有源区上的有源区，栅极绝缘层，电荷存储层，栅极电介质层和栅电极层的衬底结构。该方法还包括在衬底结构上形成图案化的金属层，使用图案化的金属栅电极层作为掩模去除栅电极层，栅极电介质层，电荷存储层的相应部分，以形成与彼此靠一个空间。每个栅极结构包括包含电荷存储层的第二部分，栅极电介质层，栅极电极层和栅极线之一的堆叠。该方法进一步包括在拉伸该空间的栅极结构的表面上形成层间介电层，同时在该空间中形成气隙。

4. 发明公开

EP3117464A1 SEMICONDUCTOR DEVICE HAVING A GAP DEFINED THEREIN 审中-公开
标题翻译： HALBLEITERBAUELEMENT MIT EINEM DARIN DEFINITENTEN SPALT
公开(公告)号：EP3117464A1
公开(公告)日：2017-01-18
申请号：EP15710374.8
申请日：2015-03-04
申请人： Qualcomm Incorporated
发明人： XU, Jeffrey Junhao , RIM, Kern , ZHU, John Jianhong , SONG, Stanley Seungchul , BADAROGLU, Mustafa , MACHKAOUTSAN, Vladimir , YANG, Da , YEAP, Choh Fei
IPC分类号： H01L29/49 , H01L29/66 , H01L29/78
CPC分类号： H01L29/6681 , H01L29/4991 , H01L29/6653 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： In a particular embodiment, a method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap.
摘要翻译：在特定实施例中，一种方法包括在半导体器件的伪栅极上形成第一间隔结构，并在第一间隔结构上形成牺牲间隔物。该方法还包括蚀刻半导体器件的结构以形成开口，经由开口去除牺牲隔离物，以及沉积材料以限定间隙。

5. 发明公开

EP2160757A4 HIGH-K/METAL GATE MOSFET WITH REDUCED PARASITIC CAPACITANCE 有权转让
标题翻译：具有降低寄生能力的高K /金属栅极MOSFET
公开(公告)号：EP2160757A4
公开(公告)日：2010-08-04
申请号：EP08780748
申请日：2008-06-04
申请人： IBM
发明人： CHENG KANGGUO
IPC分类号： H01L21/336 , H01L29/49
CPC分类号： H01L29/4991 , H01L21/28194 , H01L29/42368 , H01L29/4983 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/66583 , Y10S438/926

6. 发明公开

EP1310000A1 A POWER MOS TRANSISTOR COMPRISING A PLURALITY OF TRANSISTOR SEGMENTS WITH DIFFERENT THRESHOLD VOLTAGES 审中-公开
标题翻译：具有不同阈值电压的多段功率MOS晶体管晶体管
公开(公告)号：EP1310000A1
公开(公告)日：2003-05-14
申请号：EP01950162.6
申请日：2001-07-09
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (publ)
发明人： MOLLER, Thomas , AF EKENSTAM, Nils , JOHANSSON, Jan , BALLARD, Timothy , LOPES, Gary , PETERNEL, Michael
IPC分类号： H01L27/088 , H01L29/78
CPC分类号： H01L29/0847 , H01L21/26586 , H01L27/088 , H01L29/1033 , H01L29/1041 , H01L29/1045 , H01L29/4175 , H01L29/42368 , H01L29/49 , H01L29/4983 , H01L29/4991 , H01L29/7835
摘要： Linearity and/or efficiency of a power MOS transistor comprising a plurality of transistor segments connected in parallel, is improved in that at least one group of said transistor segments has a different threshold voltage than the rest of the transistor segments.

7. 发明公开

EP0734072A2 Insulated gate semiconductor device and method of manufacture 失效
标题翻译：一种半导体器件包括绝缘栅极，以及处理其制备
公开(公告)号：EP0734072A2
公开(公告)日：1996-09-25
申请号：EP96103289.3
申请日：1996-03-04
申请人： MOTOROLA, INC.
发明人： Davies, Robert B. , Sudhama, Chandrasekhara , Baker, Frank K.
IPC分类号： H01L29/423 , H01L21/336
CPC分类号： H01L29/4983 , H01L21/823857 , H01L29/1083 , H01L29/42376 , H01L29/4991 , H01L29/66659 , H01L29/7835
摘要： An insulated gate field effect transistor (10) having an reduced gate to drain capacitance and a method of manufacturing the field effect transistor (10). A dopant well (13) is formed in a semiconductor substrate (11) and a drain extension region (25) is formed in the dopant well (13). A oxide layer (26) is formed on the dopant well (13) wherein the oxide layer (26) has a thickness of at least 400 angstroms. A gate structure (61) having a gate shunt portion (32) over a thinned portion of the oxide (26) and a gate extension portion (58) over an unthinned portion of the oxide (26). The thinned portion of the oxide (26) forms a gate oxide of the field effect transistor (10) and the unthinned portion lowers a capacitance of the gate shunt portion (32) of the field effect transistor (10).

8. 发明公开

EP3203501A2 NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
公开(公告)号：EP3203501A2
公开(公告)日：2017-08-09
申请号：EP17152661.9
申请日：2017-01-23
申请人： Semiconductor Manufacturing International Corporation (Shanghai) , Semiconductor Manufacturing International Corporation (Beijing)
发明人： SONG, Changgeng
IPC分类号： H01L21/28 , H01L29/423 , H01L21/764 , H01L27/11524 , H01L27/11529 , H01L27/11536 , H01L27/11539 , H01L27/11541 , H01L27/11543
CPC分类号： H01L27/11543 , H01L21/28273 , H01L21/28282 , H01L21/764 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11536 , H01L27/11539 , H01L27/11541 , H01L27/11568 , H01L27/1157 , H01L27/11573 , H01L29/0657 , H01L29/42324 , H01L29/4234 , H01L29/4991
摘要： A method for manufacturing a semiconductor device includes providing a substrate structure having an active region, a gate insulating layer, a charge storage layer, a gate dielectric layer, and a gate electrode layer sequentially formed on the active region. The method also includes forming a patterned metal layer on the substrate structure, removing a respective portion of the gate electrode layer, the gate dielectric layer, the charge storage layer using the patterned metal gate electrode layer as a mask to form multiple gate structures separated from each other by a space. The gate structures each include a stack containing a second portion of the charge storage layer, the gate dielectric layer, the gate electrode layer, and one of the gate lines. The method further includes forming an interlayer dielectric layer on a surface of the gate structures stretching over the space while forming an air gap in the space.

9. 发明公开

EP2854180A1 Transistor MOS à espaceurs d'air 审中-公开
标题翻译：用空气隔离物MOS晶体管
公开(公告)号：EP2854180A1
公开(公告)日：2015-04-01
申请号：EP14186271.4
申请日：2014-09-24
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES , STMicroelectronics (Crolles 2) SAS , STmicroelectronics SA
发明人： Niebojewski, Heimanu , Le Royer, Cyrille , Morand, Yves , Rozeau, Olivier
IPC分类号： H01L29/49 , H01L29/51 , H01L29/66
CPC分类号： H01L29/515 , H01L29/0843 , H01L29/4983 , H01L29/4991 , H01L29/51 , H01L29/6653 , H01L29/6656 , H01L29/66575 , H01L29/66628 , H01L29/78
摘要： L'invention concerne un transistor MOS dont la couche d'isolant de grille (10) en un matériau à forte constante diélectrique se prolonge, à épaisseur constante, sous et en contact d'espaceurs à faible constante diélectrique (7).

10. 发明授权

EP2160757B1 HIGH-K/METAL GATE MOSFET WITH REDUCED PARASITIC CAPACITANCE 有权转让
标题翻译：高k /金属栅MOSFET具有降低的寄生电容
公开(公告)号：EP2160757B1
公开(公告)日：2013-10-16
申请号：EP08780748.3
申请日：2008-06-04
申请人： International Business Machines Corporation
发明人： CHENG, Kangguo
IPC分类号： H01L29/423 , H01L21/28 , H01L29/51
CPC分类号： H01L29/4991 , H01L21/28194 , H01L29/42368 , H01L29/4983 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/66583 , Y10S438/926

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